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Message-ID: <ZiKFNllT9tMHlH7M@smile.fi.intel.com>
Date: Fri, 19 Apr 2024 17:52:38 +0300
From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To: "Konstantin P." <ria.freelander@...il.com>
Cc: Krzysztof Kozlowski <krzk@...nel.org>, Conor Dooley <conor@...nel.org>,
	Konstantin Pugin <rilian.la.te@...ru>,
	Vladimir Zapolskiy <vz@...ia.com>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Jiri Slaby <jirislaby@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Hugo Villeneuve <hvilleneuve@...onoff.com>,
	Lech Perczak <lech.perczak@...lingroup.com>,
	Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>,
	Thomas Gleixner <tglx@...utronix.de>, linux-kernel@...r.kernel.org,
	linux-serial@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v4 2/3] dt-bindings: sc16is7xx: Add compatible line for
 XR20M1172 UART

On Fri, Apr 19, 2024 at 05:34:44PM +0300, Konstantin P. wrote:
> On Fri, Apr 19, 2024 at 5:24 PM Krzysztof Kozlowski <krzk@...nel.org> wrote:
> > On 19/04/2024 16:17, Konstantin P. wrote:

..

> > Commits must stand on their own. Cover letter is not merged. This is the
> > place where you add new hardware, so here you describe and explain the
> > hardware.
> 
> It is also described in patch 3 in the series. I need to repeat this
> description in patch 2 too?
> 
> Cite from patch 3:
> 
> XR20M1172 register set is mostly compatible with SC16IS762, but it has
> a support for additional division rates of UART with special DLD register.

The point is, if I got it correctly, to have a few words in the description
of the DT binding itself, so whoever reads the bindings (w/o even accessing
the Git history of the project) may understand this.

-- 
With Best Regards,
Andy Shevchenko



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