| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20240420-dpu-format-v2-7-9e93226cbffd@linaro.org>
Date: Sat, 20 Apr 2024 07:01:04 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Rob Clark <robdclark@...il.com>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>, Sean Paul <sean@...rly.run>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Subject: [PATCH v2 7/9] drm/msm: convert msm_format::unpack_align_msb to
the flag
Instead of having a u8 or bool field unpack_align_msb, convert it to the
flag, this save space in the tables and allows us to handle all booleans
in the same way.
Reviewed-by: Abhinav Kumar <quic_abhinavk@...cinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 12 ++----------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +-
drivers/gpu/drm/msm/disp/mdp_format.h | 4 ++--
4 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 705b91582b0f..2bb1584920c6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -43,7 +43,6 @@ bp, flg, fm, np) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
- .unpack_align_msb = 0, \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
@@ -64,7 +63,6 @@ alpha, bp, flg, fm, np, th) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
- .unpack_align_msb = 0, \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
@@ -86,7 +84,6 @@ alpha, chroma, count, bp, flg, fm, np) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 0, \
.unpack_count = count, \
.bpp = bp, \
.fetch_mode = fm, \
@@ -106,7 +103,6 @@ alpha, chroma, count, bp, flg, fm, np) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 0, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
@@ -127,7 +123,6 @@ flg, fm, np, th) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 0, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
@@ -147,11 +142,10 @@ flg, fm, np, th) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 1, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -168,11 +162,10 @@ flg, fm, np, th) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 1, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -190,7 +183,6 @@ flg, fm, np) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 0, \
.unpack_count = 1, \
.bpp = bp, \
.fetch_mode = fm, \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index d411d70b8cd8..f4b4cd084282 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -264,7 +264,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
(fmt->element[1] << 8) | (fmt->element[0] << 0);
src_format |= ((fmt->unpack_count - 1) << 12) |
((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) |
- (fmt->unpack_align_msb << 18) |
+ ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB ? 1 : 0) << 18) |
((fmt->bpp - 1) << 9);
if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index 19163634855f..93ff01c889b5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -97,7 +97,7 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
(fmt->element[1] << 8) |
(fmt->element[0] << 0);
- dst_format |= (fmt->unpack_align_msb << 18) |
+ dst_format |= ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB ? 1 : 0) << 18) |
((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) |
((fmt->unpack_count - 1) << 12) |
((fmt->bpp - 1) << 9);
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.h b/drivers/gpu/drm/msm/disp/mdp_format.h
index 18b2822dd552..d17f63c045a7 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.h
+++ b/drivers/gpu/drm/msm/disp/mdp_format.h
@@ -15,12 +15,14 @@ enum msm_format_flags {
MSM_FORMAT_FLAG_DX_BIT,
MSM_FORMAT_FLAG_COMPRESSED_BIT,
MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT,
+ MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT,
};
#define MSM_FORMAT_FLAG_YUV BIT(MSM_FORMAT_FLAG_YUV_BIT)
#define MSM_FORMAT_FLAG_DX BIT(MSM_FORMAT_FLAG_DX_BIT)
#define MSM_FORMAT_FLAG_COMPRESSED BIT(MSM_FORMAT_FLAG_COMPRESSED_BIT)
#define MSM_FORMAT_FLAG_UNPACK_TIGHT BIT(MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT)
+#define MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB BIT(MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT)
/**
* struct msm_format: defines the format configuration
@@ -29,7 +31,6 @@ enum msm_format_flags {
* @fetch_type: how the color components are packed in pixel format
* @chroma_sample: chroma sub-samplng type
* @alpha_enable: whether the format has an alpha channel
- * @unpack_align_msb: unpack aligned to LSB or MSB
* @unpack_count: number of the components to unpack
* @bpp: bytes per pixel
* @flags: usage bit flags
@@ -45,7 +46,6 @@ struct msm_format {
enum mdp_fetch_type fetch_type;
enum mdp_chroma_samp_type chroma_sample;
bool alpha_enable;
- u8 unpack_align_msb;
u8 unpack_count;
u8 bpp;
unsigned long flags;
--
2.39.2
Powered by blists - more mailing lists