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Message-ID: <20240422164035.1045501-4-quic_sibis@quicinc.com>
Date: Mon, 22 Apr 2024 22:10:33 +0530
From: Sibi Sankar <quic_sibis@...cinc.com>
To: <sudeep.holla@....com>, <cristian.marussi@....com>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <jassisinghbrar@...il.com>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<dmitry.baryshkov@...aro.org>
CC: <linux-kernel@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <quic_rgottimu@...cinc.com>,
<quic_kshivnan@...cinc.com>, <quic_sibis@...cinc.com>,
<conor+dt@...nel.org>, <quic_gkohli@...cinc.com>,
<quic_nkela@...cinc.com>, <quic_psodagud@...cinc.com>,
<abel.vesa@...aro.org>
Subject: [PATCH V4 3/5] arm64: dts: qcom: x1e80100: Resize GIC Redistributor register region
Resize the GICR register region as it currently seeps into the CPU Control
Processor mailbox RX region.
Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Signed-off-by: Sibi Sankar <quic_sibis@...cinc.com>
---
V3:
* Fix err in calc and add fixes tag. [Bjorn]
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 5f90a0b3c016..c48b3fdc550b 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -4947,7 +4947,7 @@ apps_smmu: iommu@...00000 {
intc: interrupt-controller@...00000 {
compatible = "arm,gic-v3";
reg = <0 0x17000000 0 0x10000>, /* GICD */
- <0 0x17080000 0 0x480000>; /* GICR * 12 */
+ <0 0x17080000 0 0x300000>; /* GICR * 12 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
--
2.34.1
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