linux-kernel - Re: [PATCH v5 3/3] serial: sc16is7xx: add support for EXAR XR20M1172 UART

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [day] [month] [year] [list]

Message-ID: <2be75d82-0427-4c06-adfc-a59a804ce337@kernel.org>
Date: Mon, 22 Apr 2024 22:45:47 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: "Konstantin P." <ria.freelander@...il.com>,
 Jiri Slaby <jirislaby@...nel.org>
Cc: Konstantin Pugin <rilian.la.te@...ru>, Conor Dooley <conor@...nel.org>,
 lkp@...el.com, Vladimir Zapolskiy <vz@...ia.com>,
 Rob Herring <robh@...nel.org>, jcmvbkbc@...il.com,
 nicolas.ferre@...rochip.com, manikanta.guntupalli@....com, corbet@....net,
 ychuang3@...oton.com, u.kleine-koenig@...gutronix.de,
 Maarten.Brock@...ls.nl, Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
 Jernej Skrabec <jernej.skrabec@...il.com>,
 Herve Codina <herve.codina@...tlin.com>,
 Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
 Hugo Villeneuve <hvilleneuve@...onoff.com>,
 Lech Perczak <lech.perczak@...lingroup.com>,
 Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>,
 linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org
Subject: Re: [PATCH v5 3/3] serial: sc16is7xx: add support for EXAR XR20M1172
 UART

On 22/04/2024 22:35, Konstantin P. wrote:
> On Mon, Apr 22, 2024, 23:11 Jiri Slaby <jirislaby@...nel.org> wrote:
> 
>> On 22. 04. 24, 14:00, Konstantin P. wrote:
>>> On Mon, Apr 22, 2024 at 9:30 AM Jiri Slaby <jirislaby@...nel.org> wrote:
>>>>
>>>> On 20. 04. 24, 20:22, Konstantin Pugin wrote:
>>>>> From: Konstantin Pugin <ria.freelander@...il.com>
>>>>>
>>>>> XR20M1172 register set is mostly compatible with SC16IS762, but it has
>>>>> a support for additional division rates of UART with special DLD
>> register.
>>>>> So, add handling this register by appropriate devicetree bindings.
>>>> ...
>>>>> --- a/drivers/tty/serial/sc16is7xx.c
>>>>> +++ b/drivers/tty/serial/sc16is7xx.c
>>>> ...
>>>>> @@ -555,18 +578,43 @@ static bool sc16is7xx_regmap_noinc(struct device
>> *dev, unsigned int reg)
>>>>>        return reg == SC16IS7XX_RHR_REG;
>>>>>    }
>>>>>
>>>>> +static bool sc16is7xx_has_dld(struct device *dev)
>>>>> +{
>>>>> +             struct sc16is7xx_port *s = dev_get_drvdata(dev);
>>>>> +
>>>>> +             if (s->devtype == &xr20m1172_devtype)
>>>>> +                     return true;
>>>>> +             return false;
>>>>
>>>> :) so this should simply be:
>>>>
>>>> return s->devtype == &xr20m1172_devtype;
>>>>
>>> I especially want to avoid this construction, because it will lead to
>>> idea than we does not have other
>>> DLD-capable UARTS, which is simply not true, there is, for example,
>>> XR20M1280 UART, which has roughly the same register set
>>> (
>> https://www.alldatasheet.com/datasheet-pdf/pdf/445109/EXAR/XR20M1280.html
>> ).
>>> I simply do not have other devices, so I do not
>>> want to risk sending untested patches upstream.
>>
>> Sorry, what?
>>
>> --
>> js
>> suse labs
>>
> 
> I do not wish those function to be less generic than I did. If you think
> this change is required - I will change. But if it would be okay without a
> change - I prefer to stay as is.

The code does exactly the same, so what do you mean "less generic"? What
does it even mean?

Best regards,
Krzysztof