linux-kernel - Re: [PATCH v3 2/3] PCI: qcom: Add equalization settings for 16GT/s

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <3f595432-83ad-4513-a24e-87e8ed45eba6@linaro.org>
Date: Tue, 23 Apr 2024 00:59:05 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Shashank Babu Chinta Venkata <quic_schintav@...cinc.com>,
 agross@...nel.org, andersson@...nel.org, mani@...nel.org
Cc: quic_msarkar@...cinc.com, quic_kraravin@...cinc.com,
 Lorenzo Pieralisi <lpieralisi@...nel.org>,
 Krzysztof Wilczyński <kw@...ux.com>,
 Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
 Jingoo Han <jingoohan1@...il.com>,
 Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
 Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
 Serge Semin <fancer.lancer@...il.com>,
 Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
 Conor Dooley <conor.dooley@...rochip.com>, linux-kernel@...r.kernel.org,
 linux-pci@...r.kernel.org, linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH v3 2/3] PCI: qcom: Add equalization settings for 16GT/s



On 4/19/24 02:09, Shashank Babu Chinta Venkata wrote:
> GEN3_RELATED_OFFSET is being used to determine data rate of shadow
> registers. Select data rate as 16GT/s and set appropriate equilization
> settings to improve link stability for 16GT/s data rate.
> 
> Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@...cinc.com>
> ---

[...]

> +	reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF);
> +	reg = GEN3_EQ_FMDC_T_MIN_PHASE23(0) |
> +		GEN3_EQ_FMDC_N_EVALS(0xD) |
> +		GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA(0x5) |
> +		GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA(0x5);
> +	dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg);
> +
> +	reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
> +	reg = GEN3_EQ_CONTROL_OFF_FB_MODE(0) |
> +		GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE(0) |
> +		GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL(0) |
> +		GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC(0);
> +	dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg);

Also, any chance we could get some explanations as to what these magic values mean?

Preferably in the form of a #define for each one

Konrad