linux-kernel - Re: [PATCH v21 0/9] Add multiport support for DWC3 controllers

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Message-ID:
 <SHXPR01MB0863AA6AE7B391F26EF882ADE612A@SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn>
Date: Mon, 22 Apr 2024 01:21:07 +0000
From: Minda Chen <minda.chen@...rfivetech.com>
To: Krishna Kurapati <quic_kriskura@...cinc.com>, Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@...aro.org>, Rob Herring <robh@...nel.org>, Bjorn
 Andersson <andersson@...nel.org>, Wesley Cheng <quic_wcheng@...cinc.com>,
	Konrad Dybcio <konrad.dybcio@...aro.org>, Greg Kroah-Hartman
	<gregkh@...uxfoundation.org>, Conor Dooley <conor+dt@...nel.org>, Thinh
 Nguyen <Thinh.Nguyen@...opsys.com>, Felipe Balbi <balbi@...nel.org>, Johan
 Hovold <johan@...nel.org>
CC: "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-arm-msm@...r.kernel.org" <linux-arm-msm@...r.kernel.org>,
	"linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"quic_ppratap@...cinc.com" <quic_ppratap@...cinc.com>,
	"quic_jackp@...cinc.com" <quic_jackp@...cinc.com>
Subject: Re: [PATCH v21 0/9] Add multiport support for DWC3 controllers

> 
> Currently the DWC3 driver supports only single port controller which requires at
> most two PHYs ie HS and SS PHYs. There are SoCs that has
> DWC3 controller with multiple ports that can operate in host mode.
> Some of the port supports both SS+HS and other port supports only HS mode.
> 
> This change primarily refactors the Phy logic in core driver to allow multiport
> support with Generic Phy's.
> 
> The DWC3 controller supports up to 15 High-Speed phys and 4 SuperSpeed phys.
> The multiport controller in Qualcomm SA8295P is paired with two High-Speed +
> SuperSpeed and two High-Speed-only ports. It is assumed that the N
> SuperSpeed PHYs are paired with the first N High-Speed PHYs.
> 
Hi All, Thinh
Can DW multiple port host patches be (patch 1-4) accepted first?  Other multiport
vendor will use this.