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Message-ID: <b3f2fad7-85aa-d1db-46ab-b3debd84caa7@linux.intel.com>
Date: Tue, 23 Apr 2024 16:47:53 +0300 (EEST)
From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To: Aapo Vienamo <aapo.vienamo@...ux.intel.com>
cc: Linus Walleij <linus.walleij@...aro.org>,
Bartosz Golaszewski <brgl@...ev.pl>, Andy Shevchenko <andy@...nel.org>,
linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
Mika Westerberg <mika.westerberg@...ux.intel.com>,
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Subject: Re: [PATCH] gpio: Add Intel Granite Rapids-D vGPIO driver
On Fri, 19 Apr 2024, Aapo Vienamo wrote:
> This driver provides a basic GPIO driver for the Intel Granite Rapids-D
> virtual GPIOs. On SoCs with limited physical pins on the package, the
> physical pins controlled by this driver would be exposed on an external
> device such as a BMC or CPLD.
>
> Signed-off-by: Aapo Vienamo <aapo.vienamo@...ux.intel.com>
> Reviewed-by: Mika Westerberg <mika.westerberg@...ux.intel.com>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
> diff --git a/drivers/gpio/gpio-graniterapids.c b/drivers/gpio/gpio-graniterapids.c
> new file mode 100644
> index 000000000000..61bcafe1985e
> --- /dev/null
> +++ b/drivers/gpio/gpio-graniterapids.c
> @@ -0,0 +1,382 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Intel Granite Rapids-D vGPIO driver
> + *
> + * Copyright (c) 2024, Intel Corporation.
> + *
> + * Author: Aapo Vienamo <aapo.vienamo@...ux.intel.com>
> + */
> +
> +#include <linux/array_size.h>
> +#include <linux/bitmap.h>
> +#include <linux/cleanup.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/gfp_types.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +#include <linux/math.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/overflow.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm.h>
> +#include <linux/spinlock.h>
> +#include <linux/types.h>
> +
> +#include <linux/gpio/driver.h>
> +
> +#define GNR_NUM_PINS 128
> +#define GNR_PINS_PER_REG 32
> +#define GNR_NUM_REGS DIV_ROUND_UP(GNR_NUM_PINS, GNR_PINS_PER_REG)
> +
> +#define GNR_CFG_BAR 0x00
> +#define GNR_CFG_LOCK_OFFSET 0x04
> +#define GNR_GPI_STATUS_OFFSET 0x20
> +#define GNR_GPI_ENABLE_OFFSET 0x24
> +
> +#define GNR_CFG_DW_RX_MASK (3 << 22)
GENMASK()
+ #include <linux/bits.h>
> +#define GNR_CFG_DW_RX_DISABLE (2 << 22)
> +#define GNR_CFG_DW_RX_EDGE (1 << 22)
> +#define GNR_CFG_DW_RX_LEVEL (0 << 22)
FIELD_PREP(GNR_CFG_DW_RX_MASK, xx) x 3
> +#define GNR_CFG_DW_RXDIS BIT(4)
> +#define GNR_CFG_DW_TXDIS BIT(3)
> +#define GNR_CFG_DW_RXSTATE BIT(1)
> +#define GNR_CFG_DW_TXSTATE BIT(0)
These require #include <linux/bits.h> (just pointing this out so you know
in future, you'll need to add it anyway for GENMASK() as mentioned above).
--
i.
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