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Message-ID: <691e50b7-1c1a-478a-815b-fb2a6bfdae8f@amd.com>
Date: Tue, 23 Apr 2024 08:25:45 +0200
From: Michal Simek <michal.simek@....com>
To: Sean Anderson <sean.anderson@...ux.dev>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
linux-phy@...ts.infradead.org
Cc: Vinod Koul <vkoul@...nel.org>, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Kishon Vijay Abraham I <kishon@...nel.org>
Subject: Re: [PATCH 2/3] phy: zynqmp: Don't wait for PLL lock on nonzero PCIe
lanes
On 4/22/24 20:58, Sean Anderson wrote:
> Similarly to DisplayPort, nonzero PCIe lanes never achieve PLL lock [1].
What is this [1] for?
M
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