linux-kernel - Re: [External] Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

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Message-ID: <CAEEQ3wkDMuu+jh56YB3G0vY_ENdUjDL6byMsJXd0C9aQu1FZKw@mail.gmail.com>
Date: Tue, 23 Apr 2024 19:03:40 +0800
From: yunhui cui <cuiyunhui@...edance.com>
To: Jeremy Linton <jeremy.linton@....com>
Cc: rafael@...nel.org, lenb@...nel.org, linux-acpi@...r.kernel.org, 
	linux-kernel@...r.kernel.org, paul.walmsley@...ive.com, palmer@...belt.com, 
	aou@...s.berkeley.edu, linux-riscv@...ts.infradead.org, bhelgaas@...gle.com, 
	james.morse@....com, jhugo@...eaurora.org, john.garry@...wei.com, 
	Jonathan.Cameron@...wei.com, pierre.gondois@....com, sudeep.holla@....com, 
	tiantao6@...wei.com, Palmer Dabbelt <palmer@...osinc.com>
Subject: Re: [External] Re: [PATCH v4 2/3] riscv: cacheinfo: initialize
 cacheinfo's level and type from ACPI PPTT

Hi Palmer,

On Fri, Apr 19, 2024 at 11:29 PM Jeremy Linton <jeremy.linton@....com> wrote:
>
> Hi,
>
> On 4/17/24 22:43, Yunhui Cui wrote:
> > Before cacheinfo can be built correctly, we need to initialize level
> > and type. Since RSIC-V currently does not have a register group that
> > describes cache-related attributes like ARM64, we cannot obtain them
> > directly, so now we obtain cache leaves from the ACPI PPTT table
> > (acpi_get_cache_info()) and set the cache type through split_levels.
> >
> > Suggested-by: Jeremy Linton <jeremy.linton@....com>
> > Suggested-by: Sudeep Holla <sudeep.holla@....com>
> > Signed-off-by: Yunhui Cui <cuiyunhui@...edance.com>
> > ---
> >   arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++
> >   1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
> > index 30a6878287ad..e47a1e6bd3fe 100644
> > --- a/arch/riscv/kernel/cacheinfo.c
> > +++ b/arch/riscv/kernel/cacheinfo.c
> > @@ -6,6 +6,7 @@
> >   #include <linux/cpu.h>
> >   #include <linux/of.h>
> >   #include <asm/cacheinfo.h>
> > +#include <linux/acpi.h>
> >
> >   static struct riscv_cacheinfo_ops *rv_cache_ops;
> >
> > @@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu)
> >       struct device_node *prev = NULL;
> >       int levels = 1, level = 1;
> >
> > +     if (!acpi_disabled) {
> > +             int ret, fw_levels, split_levels;
> > +
> > +             ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels);
> > +             if (ret)
> > +                     return ret;
> > +
> > +             BUG_ON((split_levels > fw_levels) ||
> > +                    (split_levels + fw_levels > this_cpu_ci->num_leaves));
> > +
> > +             for (; level <= this_cpu_ci->num_levels; level++) {
> > +                     if (level <= split_levels) {
> > +                             ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
> > +                             ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
> > +                     } else {
> > +                             ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> > +                     }
> > +             }
> > +             return 0;
> > +     }
> > +
> >       if (of_property_read_bool(np, "cache-size"))
> >               ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> >       if (of_property_read_bool(np, "i-cache-size"))
>
> Yes, looks good.
>
> Reviewed-by: Jeremy Linton <jeremy.linton@....com>
>
>
>
> Thanks,

Could you help review this patchset? Thanks.

Thanks,
Yunhui