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Message-ID: <CAL_JsqJG3NuUcfK3CGhUa1g1eHEpjmmkWQtJoiWimiCsUwhq+Q@mail.gmail.com>
Date: Thu, 25 Apr 2024 11:56:10 -0500
From: Rob Herring <robh@...nel.org>
To: Niko Pasaloukos <nikolaos.pasaloukos@...ize.com>
Cc: "krzysztof.kozlowski+dt@...aro.org" <krzysztof.kozlowski+dt@...aro.org>,
"conor+dt@...nel.org" <conor+dt@...nel.org>, "catalin.marinas@....com" <catalin.marinas@....com>,
"will@...nel.org" <will@...nel.org>, "arnd@...db.de" <arnd@...db.de>, "olof@...om.net" <olof@...om.net>,
Neil Jones <neil.jones@...ize.com>, Matt Redfearn <matthew.redfearn@...ize.com>,
James Cowgill <james.cowgill@...ize.com>,
"heiko.stuebner@...rry.de" <heiko.stuebner@...rry.de>, "shawnguo@...nel.org" <shawnguo@...nel.org>,
"macromorgan@...mail.com" <macromorgan@...mail.com>, "sre@...nel.org" <sre@...nel.org>,
"hvilleneuve@...onoff.com" <hvilleneuve@...onoff.com>,
"andre.przywara@....com" <andre.przywara@....com>, "rafal@...ecki.pl" <rafal@...ecki.pl>,
"linus.walleij@...aro.org" <linus.walleij@...aro.org>, "andersson@...nel.org" <andersson@...nel.org>,
"konrad.dybcio@...aro.org" <konrad.dybcio@...aro.org>,
"geert+renesas@...der.be" <geert+renesas@...der.be>,
"neil.armstrong@...aro.org" <neil.armstrong@...aro.org>,
"m.szyprowski@...sung.com" <m.szyprowski@...sung.com>,
"nfraprado@...labora.com" <nfraprado@...labora.com>, "u-kumar1@...com" <u-kumar1@...com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v3 4/5] arm64: Add initial support for Blaize BLZP1600 CB2
On Thu, Apr 25, 2024 at 4:15 AM Niko Pasaloukos
<nikolaos.pasaloukos@...ize.com> wrote:
>
> Adds support for the Blaize CB2 development board based on
> BLZP1600 SoC. This consists of a Carrier-Board-2 and a SoM.
>
> The blaize-blzp1600.dtsi is the common part for the SoC,
> blaize-blzp1600-som.dtsi is the common part for the SoM and
> blaize-blzp1600-cb2.dts is the board specific file.
>
> Co-developed-by: James Cowgill <james.cowgill@...ize.com>
> Signed-off-by: James Cowgill <james.cowgill@...ize.com>
> Co-developed-by: Matt Redfearn <matt.redfearn@...ize.com>
> Signed-off-by: Matt Redfearn <matt.redfearn@...ize.com>
> Co-developed-by: Neil Jones <neil.jones@...ize.com>
> Signed-off-by: Neil Jones <neil.jones@...ize.com>
> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@...ize.com>
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/blaize/Makefile | 2 +
> .../boot/dts/blaize/blaize-blzp1600-cb2.dts | 84 +++++++
> .../boot/dts/blaize/blaize-blzp1600-som.dtsi | 23 ++
> .../boot/dts/blaize/blaize-blzp1600.dtsi | 209 ++++++++++++++++++
> 5 files changed, 319 insertions(+)
> create mode 100644 arch/arm64/boot/dts/blaize/Makefile
> create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
> create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
> create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 30dd6347a929..601b6381ea0c 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -9,6 +9,7 @@ subdir-y += apm
> subdir-y += apple
> subdir-y += arm
> subdir-y += bitmain
> +subdir-y += blaize
> subdir-y += broadcom
> subdir-y += cavium
> subdir-y += exynos
> diff --git a/arch/arm64/boot/dts/blaize/Makefile b/arch/arm64/boot/dts/blaize/Makefile
> new file mode 100644
> index 000000000000..595e7a350300
> --- /dev/null
> +++ b/arch/arm64/boot/dts/blaize/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_BLAIZE_BLZP1600) += blaize-blzp1600-cb2.dtb
> diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
> new file mode 100644
> index 000000000000..0bdec7e81380
> --- /dev/null
> +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
> @@ -0,0 +1,84 @@
> +// SPDX-License-Identifier: GPL-2.0
Preferred license is GPL-2.0 plus a permissive license.
> +/*
> + * Copyright (c) 2023 Blaize, Inc. All rights reserved.
2024 now.
> + */
> +
> +/dts-v1/;
> +
> +#include "blaize-blzp1600-som.dtsi"
> +#include <dt-bindings/net/ti-dp83867.h>
> +
> +/ {
> + model = "Blaize BLZP1600 SoM1600P CB2 Development Board";
> +
> + compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200";
> + };
> +};
> +
> +&i2c0 {
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&i2c3 {
> + clock-frequency = <100000>;
> + status = "okay";
> +
> + gpio_expander: gpio@74 {
> + compatible = "ti,tca9539";
> + reg = <0x74>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-line-names = "RSP_PIN_7", /* GPIO_0 */
> + "RSP_PIN_11", /* GPIO_1 */
> + "RSP_PIN_13", /* GPIO_2 */
> + "RSP_PIN_15", /* GPIO_3 */
> + "RSP_PIN_27", /* GPIO_4 */
> + "RSP_PIN_29", /* GPIO_5 */
> + "RSP_PIN_31", /* GPIO_6 */
> + "RSP_PIN_33", /* GPIO_7 */
> + "RSP_PIN_37", /* GPIO_8 */
> + "RSP_PIN_16", /* GPIO_9 */
> + "RSP_PIN_18", /* GPIO_10 */
> + "RSP_PIN_22", /* GPIO_11 */
> + "RSP_PIN_28", /* GPIO_12 */
> + "RSP_PIN_32", /* GPIO_13 */
> + "RSP_PIN_36", /* GPIO_14 */
> + "TP31"; /* GPIO_15 */
> + };
> +
> + gpio_expander_m2: gpio@75 {
> + compatible = "ti,tca9539";
> + reg = <0x75>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-line-names = "M2_W_DIS1_N", /* GPIO_0 */
> + "M2_W_DIS2_N", /* GPIO_1 */
> + "M2_UART_WAKE_N", /* GPIO_2 */
> + "M2_COEX3", /* GPIO_3 */
> + "M2_COEX_RXD", /* GPIO_4 */
> + "M2_COEX_TXD", /* GPIO_5 */
> + "M2_VENDOR_PIN40", /* GPIO_6 */
> + "M2_VENDOR_PIN42", /* GPIO_7 */
> + "M2_VENDOR_PIN38", /* GPIO_8 */
> + "M2_SDIO_RST_N", /* GPIO_9 */
> + "M2_SDIO_WAKE_N", /* GPIO_10 */
> + "M2_PETN1", /* GPIO_11 */
> + "M2_PERP1", /* GPIO_12 */
> + "M2_PERN1", /* GPIO_13 */
> + "UIM_SWP", /* GPIO_14 */
> + "UART1_TO_RSP"; /* GPIO_15 */
> + };
> +};
> diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
> new file mode 100644
> index 000000000000..efac0d6b3d60
> --- /dev/null
> +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
> @@ -0,0 +1,23 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2023 Blaize, Inc. All rights reserved.
> + */
> +
> +#include "blaize-blzp1600.dtsi"
> +
> +/ {
> + memory@...0 {
> + device_type = "memory";
> + reg = <0x0 0x00001000 0xfffff000>;
Memory starting at 4K. That's odd. I suspect you have something
reserved there and memory really starts at 0? If so, it is preferred
that you describe memory including that 4KB and then reserve it in
/memreserve/ section or /reserved-memory node.
> + };
> +};
> +
> +/* i2c4 bus is available only on the SoM, not on the board */
> +&i2c4 {
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
> new file mode 100644
> index 000000000000..26d8943d60ab
> --- /dev/null
> +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
> @@ -0,0 +1,209 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2023 Blaize, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + enable-method = "psci";
> + reg = <0x0 0x0>;
> + next-level-cache = <&l2>;
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + enable-method = "psci";
> + reg = <0x0 0x1>;
> + next-level-cache = <&l2>;
> + };
> +
> + l2: l2-cache0 {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = /* Physical Secure PPI */
> + <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + /* Physical Non-Secure PPI */
> + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + /* Hypervisor PPI */
> + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + /* Virtual PPI */
> + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0", "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>, <&cpu1>;
> + };
> +
> + sram@0 {
> + /*
> + * On BLZP1600 there is no general purpose (non-secure) SRAM.
> + * A small DDR memory space has been reserved for general use.
> + */
> + compatible = "mmio-sram";
> + reg = <0x0 0x00000000 0x00001000>;
Ah, there it is. This isn't mmio-sram.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0 0x00000000 0x1000>;
> +
> + /* SCMI reserved buffer space on DDR space */
> + scmi0_shm: scmi-sram@800 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x800 0x80>;
> + };
Just put this node into /reserved-memory.
> + };
> +
> + firmware {
> + scmi {
> + compatible = "arm,scmi-smc";
> + arm,smc-id = <0x82002000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + shmem = <&scmi0_shm>;
> +
> + scmi_clk: protocol@14 {
> + reg = <0x14>;
> + #clock-cells = <1>;
> + };
> +
> + scmi_rst: protocol@16 {
> + reg = <0x16>;
> + #reset-cells = <1>;
> + };
> + };
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges;
It is preferred if you limit this to actual ranges needed. Looks like
nothing below 0x200000000, but I imagine this is incomplete.
Rob
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