linux-kernel - [PATCH 4/6] arm64: dts: qcom: sdx75: Add IPCC node

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Date: Fri, 26 Apr 2024 11:23:24 +0530
From: Rohit Agarwal <quic_rohiagar@...cinc.com>
To: andersson@...nel.org, konrad.dybcio@...aro.org,
        manivannan.sadhasivam@...aro.org, jassisinghbrar@...il.com,
        robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
        lee@...nel.org
Cc: linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, kernel@...cinc.com,
        Rohit Agarwal <quic_rohiagar@...cinc.com>
Subject: [PATCH 4/6] arm64: dts: qcom: sdx75: Add IPCC node

Add IPCC devicetree node to Qcom's SDX75 platform.

Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
---
 arch/arm64/boot/dts/qcom/sdx75.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
index 7dbdf8ca6de6..aae4b9ef2bb6 100644
--- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
@@ -441,6 +441,15 @@ gcc: clock-controller@...00 {
 			#power-domain-cells = <1>;
 		};
 
+		ipcc: mailbox@...000 {
+			compatible = "qcom,sdx75-ipcc", "qcom,ipcc";
+			reg = <0 0x00408000 0 0x1000>;
+			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#mbox-cells = <2>;
+		};
+
 		qupv3_id_0: geniqup@...000 {
 			compatible = "qcom,geni-se-qup";
 			reg = <0x0 0x009c0000 0x0 0x2000>;
-- 
2.25.1