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Message-ID: <CAJF2gTTeGBuL4S3cKV87w-TJTa+ZmOaPiT=+uor-PzL9jYTWAg@mail.gmail.com>
Date: Fri, 26 Apr 2024 16:15:25 +0800
From: Guo Ren <guoren@...nel.org>
To: Charlie Jenkins <charlie@...osinc.com>
Cc: Conor Dooley <conor@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Conor Dooley <conor+dt@...nel.org>,
Chen-Yu Tsai <wens@...e.org>, Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>, Conor Dooley <conor.dooley@...rochip.com>,
Evan Green <evan@...osinc.com>, Clément Léger <cleger@...osinc.com>,
Jonathan Corbet <corbet@....net>, Shuah Khan <shuah@...nel.org>, linux-riscv@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Palmer Dabbelt <palmer@...osinc.com>, linux-arm-kernel@...ts.infradead.org,
linux-sunxi@...ts.linux.dev, linux-doc@...r.kernel.org,
linux-kselftest@...r.kernel.org
Subject: Re: [PATCH v3 01/17] riscv: cpufeature: Fix thead vector hwcap removal
On Sun, Apr 21, 2024 at 9:04 AM Charlie Jenkins <charlie@...osinc.com> wrote:
>
> The riscv_cpuinfo struct that contains mvendorid and marchid is not
> populated until all harts are booted which happens after the DT parsing.
> Use the vendorid/archid values from the DT if available or assume all
> harts have the same values as the boot hart as a fallback.
>
> Fixes: d82f32202e0d ("RISC-V: Ignore V from the riscv,isa DT property on older T-Head CPUs")
> Signed-off-by: Charlie Jenkins <charlie@...osinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
> arch/riscv/include/asm/sbi.h | 2 ++
> arch/riscv/kernel/cpu.c | 40 ++++++++++++++++++++++++++++++++++++----
> arch/riscv/kernel/cpufeature.c | 12 ++++++++++--
> 3 files changed, 48 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 6e68f8dff76b..0fab508a65b3 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -370,6 +370,8 @@ static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1
> static inline void sbi_init(void) {}
> #endif /* CONFIG_RISCV_SBI */
>
> +unsigned long riscv_get_mvendorid(void);
> +unsigned long riscv_get_marchid(void);
> unsigned long riscv_cached_mvendorid(unsigned int cpu_id);
> unsigned long riscv_cached_marchid(unsigned int cpu_id);
> unsigned long riscv_cached_mimpid(unsigned int cpu_id);
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index d11d6320fb0d..c1f3655238fd 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -139,6 +139,34 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
> return -1;
> }
>
> +unsigned long __init riscv_get_marchid(void)
> +{
> + struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo);
> +
> +#if IS_ENABLED(CONFIG_RISCV_SBI)
> + ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid();
> +#elif IS_ENABLED(CONFIG_RISCV_M_MODE)
> + ci->marchid = csr_read(CSR_MARCHID);
> +#else
> + ci->marchid = 0;
> +#endif
> + return ci->marchid;
> +}
> +
> +unsigned long __init riscv_get_mvendorid(void)
> +{
> + struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo);
> +
> +#if IS_ENABLED(CONFIG_RISCV_SBI)
> + ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();
> +#elif IS_ENABLED(CONFIG_RISCV_M_MODE)
> + ci->mvendorid = csr_read(CSR_MVENDORID);
> +#else
> + ci->mvendorid = 0;
> +#endif
> + return ci->mvendorid;
> +}
> +
> DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
>
> unsigned long riscv_cached_mvendorid(unsigned int cpu_id)
> @@ -170,12 +198,16 @@ static int riscv_cpuinfo_starting(unsigned int cpu)
> struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo);
>
> #if IS_ENABLED(CONFIG_RISCV_SBI)
> - ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();
> - ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid();
> + if (!ci->mvendorid)
> + ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();
> + if (!ci->marchid)
> + ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid();
> ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid();
> #elif IS_ENABLED(CONFIG_RISCV_M_MODE)
> - ci->mvendorid = csr_read(CSR_MVENDORID);
> - ci->marchid = csr_read(CSR_MARCHID);
> + if (!ci->mvendorid)
> + ci->mvendorid = csr_read(CSR_MVENDORID);
> + if (!ci->marchid)
> + ci->marchid = csr_read(CSR_MARCHID);
> ci->mimpid = csr_read(CSR_MIMPID);
> #else
> ci->mvendorid = 0;
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 3ed2359eae35..c6e27b45e192 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -490,6 +490,8 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap)
> struct acpi_table_header *rhct;
> acpi_status status;
> unsigned int cpu;
> + u64 boot_vendorid;
> + u64 boot_archid;
>
> if (!acpi_disabled) {
> status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
> @@ -497,6 +499,13 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap)
> return;
> }
>
> + /*
> + * Naively assume that all harts have the same mvendorid/marchid as the
> + * boot hart.
> + */
> + boot_vendorid = riscv_get_mvendorid();
> + boot_archid = riscv_get_marchid();
> +
> for_each_possible_cpu(cpu) {
> struct riscv_isainfo *isainfo = &hart_isa[cpu];
> unsigned long this_hwcap = 0;
> @@ -544,8 +553,7 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap)
> * CPU cores with the ratified spec will contain non-zero
> * marchid.
> */
> - if (acpi_disabled && riscv_cached_mvendorid(cpu) == THEAD_VENDOR_ID &&
> - riscv_cached_marchid(cpu) == 0x0) {
> + if (acpi_disabled && boot_vendorid == THEAD_VENDOR_ID && boot_archid == 0x0) {
LGTM!
Reviewed-by: Guo Ren <guoren@...nel.org>
> this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v];
> clear_bit(RISCV_ISA_EXT_v, isainfo->isa);
> }
>
> --
> 2.44.0
>
--
Best Regards
Guo Ren
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