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Message-ID: <20240426122004.2249178-5-peter.griffin@linaro.org>
Date: Fri, 26 Apr 2024 13:20:02 +0100
From: Peter Griffin <peter.griffin@...aro.org>
To: alim.akhtar@...sung.com,
avri.altman@....com,
bvanassche@....org,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
James.Bottomley@...senPartnership.com,
martin.petersen@...cle.com
Cc: linux-scsi@...r.kernel.org,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org,
linux-kernel@...r.kernel.org,
tudor.ambarus@...aro.org,
andre.draszik@...aro.org,
saravanak@...gle.com,
willmcvicker@...gle.com,
kernel-team@...roid.com,
Peter Griffin <peter.griffin@...aro.org>,
Krzysztof Kozlowski <krzk@...nel.org>
Subject: [PATCH v3 4/6] scsi: ufs: host: ufs-exynos: allow max frequencies up to 267Mhz
Platforms such as Tensor gs101 the pclk frequency is 267Mhz.
Increase PCLK_AVAIL_MAX so we don't fail the frequency check.
Signed-off-by: Peter Griffin <peter.griffin@...aro.org>
Acked-by: Krzysztof Kozlowski <krzk@...nel.org>
Tested-by: Will McVicker <willmcvicker@...gle.com>
---
drivers/ufs/host/ufs-exynos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
index acf07cc54684..7acc13914100 100644
--- a/drivers/ufs/host/ufs-exynos.h
+++ b/drivers/ufs/host/ufs-exynos.h
@@ -116,7 +116,7 @@ struct exynos_ufs;
#define PA_HIBERN8TIME_VAL 0x20
#define PCLK_AVAIL_MIN 70000000
-#define PCLK_AVAIL_MAX 167000000
+#define PCLK_AVAIL_MAX 267000000
struct exynos_ufs_uic_attr {
/* TX Attributes */
--
2.44.0.769.g3c40516874-goog
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