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Message-ID: <b2c02eb9-0940-4770-a4b7-22d2af8078db@arm.com>
Date: Fri, 26 Apr 2024 16:07:56 +0100
From: James Clark <james.clark@....com>
To: Arnaldo Carvalho de Melo <acme@...nel.org>,
Tanmay Jagdale <tanmay@...vell.com>
Cc: john.g.garry@...cle.com, will@...nel.org, mike.leach@...aro.org,
leo.yan@...ux.dev, suzuki.poulose@....com, peterz@...radead.org,
mingo@...hat.com, alexander.shishkin@...ux.intel.com, jolsa@...nel.org,
irogers@...gle.com, adrian.hunter@...el.com,
linux-arm-kernel@...ts.infradead.org, coresight@...ts.linaro.org,
linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
sgoutham@...vell.com, gcherian@...vell.com, lcherian@...vell.com
Subject: Re: [PATCH V2 0/2] Fix Coresight instruction synthesis logic
On 25/04/2024 19:54, Arnaldo Carvalho de Melo wrote:
> On Thu, Apr 04, 2024 at 11:37:29PM +0530, Tanmay Jagdale wrote:
>> When we use perf to catpure Coresight trace and generate instruction
>> trace using 'perf script', we get the following output:
>>
>> # perf record -e cs_etm/@..._etr0/ -C 9 taskset -c 9 sleep 1
>> # perf script --itrace=i1ns --ns -Fcomm,tid,pid,time,cpu,event,ip,sym,addr,symoff,flags,callindent
>
> Applies cleanly, can some Coresight people review this and provide a
> Reviewed-by?
>
> Thanks!
>
Reviewed-by: James Clark <james.clark@....com>
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