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Message-ID: <171424646112.1448451.8203210233277643102.b4-ty@kernel.org>
Date: Sat, 27 Apr 2024 14:34:21 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Vinod Koul <vkoul@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>
Cc: Marijn Suijten <marijn.suijten@...ainline.org>,
linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Subject: Re: [PATCH] clk: qcom: gcc-sm8450: set OPS_PARENT_ENABLE on gcc_sdcc2_apps_clk_src
On Sat, 27 Apr 2024 14:01:07 +0200, Konrad Dybcio wrote:
> Similar to how it works on other SoCs, the top frequency of the SDHCI2
> core clock is generated by a separate PLL (peculiar design choice) that
> is not guaranteed to be enabled (why does the clock framework not handle
> this by default?).
>
> Add the CLK_OPS_PARENT_ENABLE flag to make sure we're not muxing the
> RCG input to a dormant source.
>
> [...]
Applied, thanks!
[1/1] clk: qcom: gcc-sm8450: set OPS_PARENT_ENABLE on gcc_sdcc2_apps_clk_src
commit: 2ee7aabf9e25628c7bd17ed650cac84419d12eb1
Best regards,
--
Bjorn Andersson <andersson@...nel.org>
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