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Message-ID: <560140f9b402e86b4d0e54f0eaa96a5cb57cfa22.camel@linaro.org>
Date: Mon, 29 Apr 2024 21:11:28 +0100
From: André Draszik <andre.draszik@...aro.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>, Krzysztof
 Kozlowski <krzk@...nel.org>, Sylwester Nawrocki <s.nawrocki@...sung.com>,
 Alim Akhtar <alim.akhtar@...sung.com>, Linus Walleij
 <linus.walleij@...aro.org>, Rob Herring <robh@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Tomasz Figa <tomasz.figa@...il.com>,  Peter Griffin
 <peter.griffin@...aro.org>
Cc: Tudor Ambarus <tudor.ambarus@...aro.org>, Will McVicker
	 <willmcvicker@...gle.com>, Sam Protsenko <semen.protsenko@...aro.org>, 
	kernel-team@...roid.com, linux-arm-kernel@...ts.infradead.org, 
	linux-samsung-soc@...r.kernel.org, linux-gpio@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 0/2] clock support for Samsung Exynos pin controller
 (Google Tensor gs101)

On Mon, 2024-04-29 at 21:06 +0100, André Draszik wrote:
> Hi Krzysztof,
> 
> On Mon, 2024-04-29 at 19:45 +0200, Krzysztof Kozlowski wrote:
> > On 29/04/2024 19:28, Krzysztof Kozlowski wrote:
> > > 
> > > On Fri, 26 Apr 2024 14:25:13 +0100, André Draszik wrote:
> > > > This series enables clock support on the Samsung Exynos pin controller
> > > > driver.
> > > > 
> > > > This is required on Socs like Google Tensor gs101, which implement
> > > > fine-grained clock control / gating, and as such a running bus clock is
> > > > required for register access to work.
> > > > 
> > 
> > Where's the DTS?
> 
> Here: https://lore.kernel.org/r/20240429-samsung-pinctrl-busclock-dts-v1-0-5e935179f3ca@linaro.org
> 
> (I was waiting to see how the HSI2 patches pan out)

.. and potential binding feedback of course :-)



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