lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ef23ykui3axiwfkr4wi24abbuklvejx5r5wqem5cr4lq36x7py@kkxvsi3ibtbi>
Date: Mon, 29 Apr 2024 08:49:00 +0200
From: Gerd Hoffmann <kraxel@...hat.com>
To: Guenter Roeck <linux@...ck-us.net>
Cc: David Laight <David.Laight@...lab.com>, 
	Alan Stern <stern@...land.harvard.edu>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, 
	"linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2] usb: ohci: Prevent missed ohci interrupts

  Hi,

> > > +	/* repeat until all enabled interrupts are handled */
> > > +	if (ohci->rh_state != OHCI_RH_HALTED) {
> > > +		ints = ohci_readl(ohci, &regs->intrstatus);
> > > +		if (ints & ohci_readl(ohci, &regs->intrenable))
> > 
> > Doesn't the driver know which interrupts are enabled?
> > So it should be able to avoid doing two (likely) slow io reads?
> > (PCIe reads are pretty much guaranteed to be high latency.)
> 
> No, the driver does not cache intrenable.

Does the driver ever change intrenable after initialization?

PCIe reads are expensive, especially in virtual machines where this
goes vmexit to qemu, so doing that for a piece of information the
driver should have (or is able to calculate) should indeed better
be avoided.

take care,
  Gerd


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ