linux-kernel - Re: [PATCH] MIPS: Take in account load hazards for HI/LO restoring

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date: Mon, 29 Apr 2024 10:30:31 +0200
From: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
To: Siarhei Volkau <lis8215@...il.com>
Cc: linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org,
	Paul Cercueil <paul@...pouillou.net>
Subject: Re: [PATCH] MIPS: Take in account load hazards for HI/LO restoring

On Mon, Apr 29, 2024 at 10:18:57AM +0200, Thomas Bogendoerfer wrote:
> On Thu, Oct 12, 2023 at 07:20:27PM +0300, Siarhei Volkau wrote:
> > MIPS CPUs usually have 1 to 4 cycles load hazards, thus doing load
> > and right after move to HI/LO will usually stall the pipeline for
> > significant amount of time. Let's take it into account and separate
> > loads and mthi/lo in instruction sequence.
> > 
> > The patch uses t6 and t7 registers as temporaries in addition to t8.
> > 
> > The patch tries to deal with SmartMIPS, but I know little about and
> > haven't tested it.
> > 
> > Signed-off-by: Siarhei Volkau <lis8215@...il.com>
> > ---
> >  arch/mips/include/asm/stackframe.h | 22 ++++++++++++----------
> >  1 file changed, 12 insertions(+), 10 deletions(-)
> > 
> > diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
> > index a8705aef47e1..3821d91b00fd 100644
> > --- a/arch/mips/include/asm/stackframe.h
> > +++ b/arch/mips/include/asm/stackframe.h
> > @@ -308,17 +308,11 @@
> >  		jal	octeon_mult_restore
> >  #endif
> >  #ifdef CONFIG_CPU_HAS_SMARTMIPS
> > -		LONG_L	$24, PT_ACX(sp)
> > -		mtlhx	$24
> > -		LONG_L	$24, PT_HI(sp)
> > -		mtlhx	$24
> > -		LONG_L	$24, PT_LO(sp)
> > -		mtlhx	$24
> > -#elif !defined(CONFIG_CPU_MIPSR6)
> > +		LONG_L	$14, PT_ACX(sp)
> > +#endif
> > +#if defined(CONFIG_CPU_HAS_SMARTMIPS) || !defined(CONFIG_CPU_MIPSR6)
> 
> isn't that just #ifndef CONFIG_CPU_MIPSR6 ? 

and if yes, I prefer to have the same structure as for the move to
registers later like

#ifdef CONFIG_CPU_HAS_SMARTMIPS
. do the SMARTMIPS things
elif !defined(CONFIG_CPU_MIPSR6)
. do normal hi/lo
#endif

that way it's more clear whats happening depending on selected
options.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]