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Date: Mon, 29 Apr 2024 13:46:26 +0300
From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To: linux-pci@...r.kernel.org,
Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Rob Herring <robh@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>,
Andrew Lunn <andrew@...n.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Gregory Clement <gregory.clement@...tlin.com>,
Russell King <linux@...linux.org.uk>,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Cc: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
Subject: [PATCH 03/10] ARM: orion5x: Pass devfn to orion5x_pci_hw_{rd,wr}_conf()
Pass the usual devfn instead of individual components into
orion5x_pci_hw_{rd,wr}_conf() to make the change into
pci_conf1_offset() in an upcoming commit easier.
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
---
arch/arm/mach-orion5x/pci.c | 45 +++++++++++++++++++------------------
1 file changed, 23 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 77ddab90f448..6376e1db6386 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -270,15 +270,15 @@ static int orion5x_pci_local_bus_nr(void)
return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
}
-static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
- u32 where, u32 size, u32 *val)
+static int orion5x_pci_hw_rd_conf(int bus, u8 devfn, u32 where,
+ u32 size, u32 *val)
{
unsigned long flags;
spin_lock_irqsave(&orion5x_pci_lock, flags);
writel(PCI_CONF_BUS(bus) |
- PCI_CONF_DEV(dev) | ORION5X_PCI_CONF_REG(where) |
- ORION5X_PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
+ PCI_CONF_DEV(PCI_SLOT(devfn)) | ORION5X_PCI_CONF_REG(where) |
+ ORION5X_PCI_CONF_FUNC(PCI_FUNC(devfn)) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
*val = readl(PCI_CONF_DATA);
@@ -292,8 +292,8 @@ static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
return PCIBIOS_SUCCESSFUL;
}
-static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
- u32 where, u32 size, u32 val)
+static int orion5x_pci_hw_wr_conf(int bus, u8 devfn, u32 where,
+ u32 size, u32 val)
{
unsigned long flags;
int ret = PCIBIOS_SUCCESSFUL;
@@ -301,8 +301,8 @@ static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
spin_lock_irqsave(&orion5x_pci_lock, flags);
writel(PCI_CONF_BUS(bus) |
- PCI_CONF_DEV(dev) | ORION5X_PCI_CONF_REG(where) |
- ORION5X_PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
+ PCI_CONF_DEV(PCI_SLOT(devfn)) | ORION5X_PCI_CONF_REG(where) |
+ ORION5X_PCI_CONF_FUNC(PCI_FUNC(devfn)) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
if (size == 4) {
__raw_writel(val, PCI_CONF_DATA);
@@ -347,8 +347,7 @@ static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
return PCIBIOS_DEVICE_NOT_FOUND;
}
- return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
- PCI_FUNC(devfn), where, size, val);
+ return orion5x_pci_hw_rd_conf(bus->number, devfn, where, size, val);
}
static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
@@ -357,8 +356,7 @@ static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
if (!orion5x_pci_valid_config(bus->number, devfn))
return PCIBIOS_DEVICE_NOT_FOUND;
- return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
- PCI_FUNC(devfn), where, size, val);
+ return orion5x_pci_hw_wr_conf(bus->number, devfn, where, size, val);
}
static struct pci_ops pci_ops = {
@@ -375,12 +373,14 @@ static void __init orion5x_pci_set_bus_nr(int nr)
* PCI-X mode
*/
u32 pcix_status, bus, dev;
+ u8 devfn;
bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
- orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
+ devfn = PCI_DEVFN(dev, 0);
+ orion5x_pci_hw_rd_conf(bus, devfn, PCIX_STAT, 4, &pcix_status);
pcix_status &= ~PCIX_STAT_BUS_MASK;
pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
- orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
+ orion5x_pci_hw_wr_conf(bus, devfn, PCIX_STAT, 4, pcix_status);
} else {
/*
* PCI Conventional mode
@@ -393,15 +393,16 @@ static void __init orion5x_pci_set_bus_nr(int nr)
static void __init orion5x_pci_master_slave_enable(void)
{
- int bus_nr, func, reg;
+ int bus_nr, reg;
+ u8 devfn;
u32 val;
bus_nr = orion5x_pci_local_bus_nr();
- func = PCI_CONF_FUNC_STAT_CMD;
+ devfn = PCI_DEVFN(0, PCI_CONF_FUNC_STAT_CMD);
reg = PCI_CONF_REG_STAT_CMD;
- orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
+ orion5x_pci_hw_rd_conf(bus_nr, devfn, reg, 4, &val);
val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
+ orion5x_pci_hw_wr_conf(bus_nr, devfn, reg, 4, val | 0x7);
}
static void __init orion5x_setup_pci_wins(void)
@@ -424,7 +425,7 @@ static void __init orion5x_setup_pci_wins(void)
for (i = 0; i < dram->num_cs; i++) {
const struct mbus_dram_window *cs = dram->cs + i;
- u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
+ u8 devfn = PCI_DEVFN(0, PCI_CONF_FUNC_BAR_CS(cs->cs_index));
u32 reg;
u32 val;
@@ -432,15 +433,15 @@ static void __init orion5x_setup_pci_wins(void)
* Write DRAM bank base address register.
*/
reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
- orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
+ orion5x_pci_hw_rd_conf(bus, devfn, reg, 4, &val);
val = (cs->base & 0xfffff000) | (val & 0xfff);
- orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
+ orion5x_pci_hw_wr_conf(bus, devfn, reg, 4, val);
/*
* Write DRAM bank size register.
*/
reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
- orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
+ orion5x_pci_hw_wr_conf(bus, devfn, reg, 4, 0);
writel((cs->size - 1) & 0xfffff000,
PCI_BAR_SIZE_DDR_CS(cs->cs_index));
writel(cs->base & 0xfffff000,
--
2.39.2
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