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Date: Tue, 30 Apr 2024 11:38:12 -0700
From: Charlie Jenkins <charlie@...osinc.com>
To: Andrew Jones <ajones@...tanamicro.com>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>, Guo Ren <guoren@...nel.org>,
	Conor Dooley <conor@...nel.org>,
	Conor Dooley <conor.dooley@...rochip.com>,
	Clément Léger <cleger@...osinc.com>,
	Evan Green <evan@...osinc.com>,
	Palmer Dabbelt <palmer@...osinc.com>,
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 1/2] riscv: cpufeature: Fix thead vector hwcap removal

On Tue, Apr 30, 2024 at 12:07:26PM +0200, Andrew Jones wrote:
> On Mon, Apr 29, 2024 at 03:29:51PM GMT, Charlie Jenkins wrote:
> ...
> > +		 *
> > +		 * Disable vector if the boot hart has a T-Head mvendorid and an marchid of 0.
> 
> I probably would have added the 'why' to this comment, i.e. T-Head doesn't
> have standard V so things will break if we try to use it, or whatever. The
> 'what' alone is just putting the easy to read condition below into
> English, making it an unnecessary comment.

The 'why' is directly above this comment. I'll just get rid of this
addition.

- Charlie

> 
> Thanks,
> drew
> 
> >  		 */
> > -		if (acpi_disabled && riscv_cached_mvendorid(cpu) == THEAD_VENDOR_ID &&
> > -		    riscv_cached_marchid(cpu) == 0x0) {
> > +		if (acpi_disabled && boot_vendorid == THEAD_VENDOR_ID && boot_archid == 0x0) {
> >  			this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v];
> >  			clear_bit(RISCV_ISA_EXT_v, isainfo->isa);
> >  		}
> > 
> > -- 
> > 2.44.0
> > 
> > 
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@...ts.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv

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