linux-kernel - Re: [PATCH] clk: qcom: gcc-sm8450: set OPS_PARENT_ENABLE on gcc_sdcc2_apps_clk

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Message-ID: <6ba2967c6c9d24e3f1c9b76496176010.sboyd@kernel.org>
Date: Tue, 30 Apr 2024 14:26:53 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Bjorn Andersson <andersson@...nel.org>, Konrad Dybcio <konrad.dybcio@...aro.org>, Michael Turquette <mturquette@...libre.com>, Vinod Koul <vkoul@...nel.org>
Cc: Marijn Suijten <marijn.suijten@...ainline.org>, linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Subject: Re: [PATCH] clk: qcom: gcc-sm8450: set OPS_PARENT_ENABLE on gcc_sdcc2_apps_clk_src

Quoting Konrad Dybcio (2024-04-30 03:46:52)
> On 30.04.2024 2:21 AM, Stephen Boyd wrote:
> > Quoting Konrad Dybcio (2024-04-27 05:01:07)
> >> Similar to how it works on other SoCs, the top frequency of the SDHCI2
> >> core clock is generated by a separate PLL (peculiar design choice) that
> >> is not guaranteed to be enabled (why does the clock framework not handle
> >> this by default?).
> >>
> >> Add the CLK_OPS_PARENT_ENABLE flag to make sure we're not muxing the
> >> RCG input to a dormant source.
> > 
> > The RCG2 hardware hasn't required the parent to be enabled for clk
> > operations besides for the glitch-free source switch. What scenario is
> > happening here that's requiring this flag? Is the RCG forcibly enabled
> > perhaps because the bootloader has left the root enable bit set
> > (CMD_ROOT_EN)? Or are we changing the parent while the clk framework
> > thinks the clk is off when it is actually on?
> > 
> > TL;DR: This is papering over a bigger bug.
> 
> Definitely.
> 
> 
> Take a look at:
> 
> static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
>         F(400000, P_BI_TCXO, 12, 1, 4),
>         F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
>         F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
>         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
>         F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
>         { }
> };
> 
> XO and GPLL0 are more or less always on, but GPLL9 is described to only
> be used for this specific clock for this specific frequency (perhaps it
> feeds something else on the soc but that's besides the point).
> 
> Then, the parent input is changed during set_rate, but GPLL9 seems to
> never be enabled:

Is the sdcc2 RCG enabled during the set_rate?