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Date: Tue, 30 Apr 2024 13:33:15 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Alexandre Mergnat <amergnat@...libre.com>, chunkuang.hu@...nel.org
Cc: robh@...nel.org, krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
 p.zabel@...gutronix.de, airlied@...il.com, daniel@...ll.ch,
 maarten.lankhorst@...ux.intel.com, mripard@...nel.org, tzimmermann@...e.de,
 matthias.bgg@...il.com, shawn.sung@...iatek.com, yu-chang.lee@...iatek.com,
 ck.hu@...iatek.com, jitao.shi@...iatek.com, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org,
 linux-mediatek@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org,
 wenst@...omium.org, kernel@...labora.com
Subject: Re: [PATCH v2 0/3] drm/mediatek: Add support for OF graphs

Il 30/04/24 12:17, Alexandre Mergnat ha scritto:
> Hi Angelo,
> 
> On 09/04/2024 14:02, AngeloGioacchino Del Regno wrote:
>> This series was tested on MT8195 Cherry Tomato and on MT8395 Radxa
>> NIO-12L with both hardcoded paths, OF graph support and partially
>> hardcoded paths (meaning main display through OF graph and external
>> display hardcoded, because of OVL_ADAPTOR).
> 
> Is that make sense for you to add the DTS changes of these boards into this serie ?
> I asked because, IMHO, that could help to understand the serie.
> 

Yes and no... but I imagine that you're asking this because you're trying to
prepare something with a different SoC+board(s) combination :-)

In that case, I'm preventively sorry because what follows here is not 100%
perfectly tidy yet as I didn't mean to send the devicetree commits upstream
before this series got picked....

.. but there you go - I'm sure that you won't mind and that the example will
be more than good enough for you.

Please note that one of the reasons why I didn't want to add this to the series
is that the following changes show only a mere 50% of the reasons why we want OF
graph support on mediatek-drm (but mainly, it's because I didn't have time to
actually rebase etc :-P )


Cheers!
Angelo



  .../boot/dts/mediatek/mt8195-cherry.dtsi      |  65 +++++++-
  arch/arm64/boot/dts/mediatek/mt8195.dtsi      | 153 +++++++++++++++++-
  .../dts/mediatek/mt8395-radxa-nio-12l.dts     |  24 +++
  3 files changed, 231 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 86d283ffe807..b05b6bbd457c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -267,12 +267,29 @@ &auxadc {
  	status = "okay";
  };

+&dither0_out {
+	remote-endpoint = <&dsc0_in>;
+};
+
  &dp_intf0 {
  	status = "okay";

-	port {
-		dp_intf0_out: endpoint {
-			remote-endpoint = <&edp_in>;
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			dp_intf0_in: endpoint {
+				remote-endpoint = <&merge0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			dp_intf0_out: endpoint {
+				remote-endpoint = <&edp_in>;
+			};
  		};
  	};
  };
@@ -287,6 +304,27 @@ dp_intf1_out: endpoint {
  	};
  };

+&dsc0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			dsc0_in: endpoint {
+				remote-endpoint = <&dither0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			dsc0_out: endpoint {
+				remote-endpoint = <&merge0_in>;
+			};
+		};
+	};
+};
+
  &edp_tx {
  	status = "okay";

@@ -481,6 +519,27 @@ pmic@34 {
  	};
  };

+&merge0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			merge0_in: endpoint {
+				remote-endpoint = <&dsc0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			merge0_out: endpoint {
+				remote-endpoint = <&dp_intf0_in>;
+			};
+		};
+	};
+};
+
  &mfg0 {
  	domain-supply = <&mt6315_7_vbuck1>;
  };
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 88a0035a31a5..982572d7bfd8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -3077,14 +3077,6 @@ vencsys_core1: clock-controller@...00000 {
  			#clock-cells = <1>;
  		};

-		vdosys0: syscon@...1a000 {
-			compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
-			reg = <0 0x1c01a000 0 0x1000>;
-			mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
-			#clock-cells = <1>;
-		};
-
-
  		jpgenc-master {
  			compatible = "mediatek,mt8195-jpgenc";
  			power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
@@ -3143,6 +3135,38 @@ ovl0: ovl@...00000 {
  			clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
  			iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
  			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					ovl0_in: endpoint {
+						remote-endpoint = <&vdosys0_ep_main>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					ovl0_out: endpoint {
+						remote-endpoint = <&rdma0_in>;
+					};
+				};
+			};
+		};
+
+		vdosys0: syscon@...1a000 {
+			compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
+			reg = <0 0x1c01a000 0 0x1000>;
+			mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
+			#clock-cells = <1>;
+
+			port {
+				vdosys0_ep_main: endpoint {
+					remote-endpoint = <&ovl0_in>;
+				};
+			};
  		};

  		rdma0: rdma@...02000 {
@@ -3153,6 +3177,25 @@ rdma0: rdma@...02000 {
  			clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
  			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
  			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					rdma0_in: endpoint {
+						remote-endpoint = <&ovl0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					rdma0_out: endpoint {
+						remote-endpoint = <&color0_in>;
+					};
+				};
+			};
  		};

  		color0: color@...03000 {
@@ -3162,6 +3205,25 @@ color0: color@...03000 {
  			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
  			clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
  			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					color0_in: endpoint {
+						remote-endpoint = <&rdma0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					color0_out: endpoint {
+						remote-endpoint = <&ccorr0_in>;
+					};
+				};
+			};
  		};

  		ccorr0: ccorr@...04000 {
@@ -3171,6 +3233,25 @@ ccorr0: ccorr@...04000 {
  			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
  			clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
  			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					ccorr0_in: endpoint {
+						remote-endpoint = <&color0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					ccorr0_out: endpoint {
+						remote-endpoint = <&aal0_in>;
+					};
+				};
+			};
  		};

  		aal0: aal@...05000 {
@@ -3180,6 +3261,25 @@ aal0: aal@...05000 {
  			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
  			clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
  			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					aal0_in: endpoint {
+						remote-endpoint = <&ccorr0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					aal0_out: endpoint {
+						remote-endpoint = <&gamma0_in>;
+					};
+				};
+			};
  		};

  		gamma0: gamma@...06000 {
@@ -3189,6 +3289,25 @@ gamma0: gamma@...06000 {
  			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
  			clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
  			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					gamma0_in: endpoint {
+						remote-endpoint = <&aal0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					gamma0_out: endpoint {
+						remote-endpoint = <&dither0_in>;
+					};
+				};
+			};
  		};

  		dither0: dither@...07000 {
@@ -3198,6 +3317,24 @@ dither0: dither@...07000 {
  			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
  			clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
  			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dither0_in: endpoint {
+						remote-endpoint = <&gamma0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					dither0_out: endpoint {
+					};
+				};
+			};
  		};

  		dsi0: dsi@...08000 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts 
b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
index 7ab19b4e046f..b4a7dad2fea7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
@@ -1063,6 +1063,10 @@ &disp_pwm0 {
  	status = "okay";
  };

+&dither0_out {
+	remote-endpoint = <&dsi0_in>;
+};
+
  &dsi0 {
  	status = "okay";
  	#address-cells = <1>;
@@ -1089,6 +1093,25 @@ dsi_panel_in: endpoint {
  		};
  	};

+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			dsi0_in: endpoint {
+				remote-endpoint = <&dither0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			dsi_out: endpoint {
+				remote-endpoint = <&dsi_panel_in>;
+			};
+		};
+	};
+/* old hardcoded dsi stuff, disappear!
  	ports {
  		port {
  			dsi_out: endpoint {
@@ -1096,6 +1119,7 @@ dsi_out: endpoint {
  			};
  		};
  	};
+*/

  };

-- 
2.45.0


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