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Message-ID: <20240430141445.2688499-2-peter.griffin@linaro.org>
Date: Tue, 30 Apr 2024 15:14:43 +0100
From: Peter Griffin <peter.griffin@...aro.org>
To: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
alim.akhtar@...sung.com
Cc: devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org,
linux-kernel@...r.kernel.org,
tudor.ambarus@...aro.org,
andre.draszik@...aro.org,
saravanak@...gle.com,
willmcvicker@...gle.com,
kernel-team@...roid.com,
Peter Griffin <peter.griffin@...aro.org>
Subject: [PATCH v5 1/3] arm64: dts: exynos: gs101: Add the hsi2 sysreg node
This has some configuration bits such as sharability that
are required by UFS.
Signed-off-by: Peter Griffin <peter.griffin@...aro.org>
Reviewed-by: André Draszik <andre.draszik@...aro.org>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index e3b068c1a2c1..9f7635a7928e 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1320,6 +1320,12 @@ cmu_hsi2: clock-controller@...00000 {
clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
};
+ sysreg_hsi2: syscon@...20000 {
+ compatible = "google,gs101-hsi2-sysreg", "syscon";
+ reg = <0x14420000 0x10000>;
+ clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>;
+ };
+
pinctrl_hsi2: pinctrl@...40000 {
compatible = "google,gs101-pinctrl";
reg = <0x14440000 0x00001000>;
--
2.45.0.rc0.197.gbae5840b3b-goog
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