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Message-ID: <20240430142757.16872-4-quic_jkona@quicinc.com>
Date: Tue, 30 Apr 2024 19:57:52 +0530
From: Jagadeesh Kona <quic_jkona@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette
<mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring
<robh+dt@...nel.org>,
Krzysztof Kozlowski
<krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Vladimir Zapolskiy
<vladimir.zapolskiy@...aro.org>
CC: Bryan O'Donoghue <bryan.odonoghue@...aro.org>,
<linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Taniya Das
<quic_tdas@...cinc.com>,
Jagadeesh Kona <quic_jkona@...cinc.com>,
"Satya
Priya Kakitapalli" <quic_skakitap@...cinc.com>,
Ajit Pandey
<quic_ajipan@...cinc.com>,
Imran Shaik <quic_imrashai@...cinc.com>,
"Dmitry
Baryshkov" <dmitry.baryshkov@...aro.org>
Subject: [PATCH V3 3/8] clk: qcom: videocc-sm8550: Add support for videocc XO clk ares
Add support for videocc XO clk ares for consumer drivers to be
able to request this reset.
Fixes: f53153a37969 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550")
Signed-off-by: Jagadeesh Kona <quic_jkona@...cinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
---
drivers/clk/qcom/videocc-sm8550.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c
index d73f747d2474..25133cf5a2b8 100644
--- a/drivers/clk/qcom/videocc-sm8550.c
+++ b/drivers/clk/qcom/videocc-sm8550.c
@@ -10,7 +10,7 @@
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
-#include <dt-bindings/clock/qcom,sm8450-videocc.h>
+#include <dt-bindings/clock/qcom,sm8650-videocc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
@@ -380,6 +380,7 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = {
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
[VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 },
[VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 },
+ [VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 },
};
static const struct regmap_config video_cc_sm8550_regmap_config = {
--
2.43.0
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