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Message-ID: <20240501-glare-occupier-2aee6a0aab06@spud>
Date: Wed, 1 May 2024 10:30:04 +0100
From: Conor Dooley <conor@...nel.org>
To: Tomasz Jeznach <tjeznach@...osinc.com>
Cc: Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
Robin Murphy <robin.murphy@....com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Anup Patel <apatel@...tanamicro.com>,
Sunil V L <sunilvl@...tanamicro.com>,
Nick Kossifidis <mick@....forth.gr>,
Sebastien Boeuf <seb@...osinc.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, devicetree@...r.kernel.org,
iommu@...ts.linux.dev, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux@...osinc.com
Subject: Re: [PATCH v3 1/7] dt-bindings: iommu: riscv: Add bindings for
RISC-V IOMMU
On Tue, Apr 30, 2024 at 01:01:51PM -0700, Tomasz Jeznach wrote:
> Add bindings for the RISC-V IOMMU device drivers.
>
> Co-developed-by: Anup Patel <apatel@...tanamicro.com>
> Signed-off-by: Anup Patel <apatel@...tanamicro.com>
> Signed-off-by: Tomasz Jeznach <tjeznach@...osinc.com>
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
Thanks,
Conor.
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