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Message-Id: <20240502-mips_debug_ll-v3-7-3b61f30e484c@flygoat.com>
Date: Thu, 02 May 2024 10:59:34 +0100
From: Jiaxun Yang <jiaxun.yang@...goat.com>
To: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Cc: linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org,
Jiaxun Yang <jiaxun.yang@...goat.com>
Subject: [PATCH v3 7/9] MIPS: debug_ll: Implement support for AR933X uarts
Implement support for AR933X uarts which has it's own register
definition.
Signed-off-by: Jiaxun Yang <jiaxun.yang@...goat.com>
---
arch/mips/Kconfig.debug | 9 +++++++++
arch/mips/include/debug/ar933x.S | 41 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index aef116058654..a6687c503c34 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -265,6 +265,14 @@ choice
Say Y here if you want kernel low-level debugging support
on uart of alchemy SoCs.
+ config DEBUG_AR933X_UART
+ bool "Kernel low-level debugging messages via Alchemy UART"
+ depends on MIPS_ALCHEMY
+ select DEBUG_LL_UART
+ help
+ Say Y here if you want kernel low-level debugging support
+ on uart of AR933X SoCs.
+
endchoice
config DEBUG_LL_INCLUDE
@@ -303,6 +311,7 @@ config DEBUG_UART_PHYS
default 0x1fe00000 if DEBUG_LOONGSON2K_UART
default 0x10030000 if DEBUG_INGENIC_UART
default 0x11100000 if DEBUG_ALCHEMY_UART
+ default 0x18020000 if DEBUG_AR933X_UART
help
This is the physical base address of the debug UART. It must be
accessible from unmapped kernel space (i.e. KSEG1 for 32bit kernels
diff --git a/arch/mips/include/debug/ar933x.S b/arch/mips/include/debug/ar933x.S
new file mode 100644
index 000000000000..1a0449082080
--- /dev/null
+++ b/arch/mips/include/debug/ar933x.S
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023, Jiaxun Yang <jiaxun.yang@...goat.com>
+ * MIPS Low level debug include file for ar933x UART
+ */
+
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+#include <asm/mach-ath79/ar933x_uart.h>
+
+#define DEBUG_LL_UART
+
+#define UART_BASE CKSEG1ADDR(CONFIG_DEBUG_UART_PHYS)
+
+# define UART_L lw
+# define UART_S sw
+
+ .macro addruart,rd,rx
+ PTR_LA \rd, UART_BASE
+ .endm
+
+ .macro senduart,rd,rx
+ UART_S \rd, AR933X_UART_DATA_REG(\rx)
+ .endm
+
+ /* CTS and RDY are handled by AR933X_UART_DATA_TX_CSR as well */
+ .macro busyuart,rd,rx
+1002:
+ UART_L \rd, AR933X_UART_DATA_REG(\rx)
+ andi \rd, \rd, (AR933X_UART_DATA_TX_CSR)
+ xori \rd, (AR933X_UART_DATA_TX_CSR)
+ bnez \rd, 1002b
+ .endm
+
+ .macro waituarttxrdy,rd,rx
+ busyuart \rd, \rx
+ .endm
+
+ .macro waituartcts,rd,rx
+ busyuart \rd, \rx
+ .endm
--
2.34.1
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