linux-kernel - Re: [PATCH 1/3] spi: spi-microchip-core: Add support for GPIO based CS

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Message-ID: <20240502-produce-gallery-3b8e17db9c01@spud>
Date: Thu, 2 May 2024 16:54:46 +0100
From: Conor Dooley <conor@...nel.org>
To: Prajna Rajendra Kumar <prajna.rajendrakumar@...rochip.com>
Cc: Mark Brown <broonie@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	linux-riscv@...ts.infradead.org, linux-spi@...r.kernel.org,
	linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
	Conor Dooley <conor.dooley@...rochip.com>,
	Daire McNamara <daire.mcnamara@...rochip.com>,
	valentina.fernandezalanis@...rochip.com
Subject: Re: [PATCH 1/3] spi: spi-microchip-core: Add support for GPIO based
 CS

On Thu, May 02, 2024 at 03:34:08PM +0100, Prajna Rajendra Kumar wrote:
> The SPI controller within the PolarFire SoC is capable of handling
> multiple CS, but only one CS line is wired in the MSS. Therefore,
> use GPIO descriptors to configure additional CS lines.
> 
> Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@...rochip.com>

Acked-by: Conor Dooley <conor.dooley@...rochip.com>

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