linux-kernel - Re: [PATCH bpf-next v2 1/2] riscv, bpf: add internal-only MOV instruction to resolve per-CPU addrs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <CANk7y0gqpAqjp-Ny6GyCsmTB5uk3UGc0uHpPr=ujOD0Rz_ogWw@mail.gmail.com>
Date: Thu, 2 May 2024 18:20:58 +0200
From: Puranjay Mohan <puranjay12@...il.com>
To: Björn Töpel <bjorn@...nel.org>
Cc: Andrii Nakryiko <andrii.nakryiko@...il.com>, Puranjay Mohan <puranjay@...nel.org>, 
	Alexei Starovoitov <ast@...nel.org>, Daniel Borkmann <daniel@...earbox.net>, 
	Andrii Nakryiko <andrii@...nel.org>, Martin KaFai Lau <martin.lau@...ux.dev>, 
	Eduard Zingerman <eddyz87@...il.com>, Song Liu <song@...nel.org>, 
	Yonghong Song <yonghong.song@...ux.dev>, John Fastabend <john.fastabend@...il.com>, 
	KP Singh <kpsingh@...nel.org>, Stanislav Fomichev <sdf@...gle.com>, Hao Luo <haoluo@...gle.com>, 
	Jiri Olsa <jolsa@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>, 
	Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, bpf@...r.kernel.org, 
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, 
	Pu Lehui <pulehui@...wei.com>
Subject: Re: [PATCH bpf-next v2 1/2] riscv, bpf: add internal-only MOV
 instruction to resolve per-CPU addrs

On Thu, May 2, 2024 at 6:18 PM Björn Töpel <bjorn@...nel.org> wrote:
>
> Andrii Nakryiko <andrii.nakryiko@...il.com> writes:
>
> > On Tue, Apr 30, 2024 at 10:58 AM Puranjay Mohan <puranjay@...nel.org> wrote:
> >>
> >> Support an instruction for resolving absolute addresses of per-CPU
> >> data from their per-CPU offsets. This instruction is internal-only and
> >> users are not allowed to use them directly. They will only be used for
> >> internal inlining optimizations for now between BPF verifier and BPF
> >> JITs.
> >>
> >> RISC-V uses generic per-cpu implementation where the offsets for CPUs
> >> are kept in an array called __per_cpu_offset[cpu_number]. RISCV stores
> >> the address of the task_struct in TP register. The first element in
> >> task_struct is struct thread_info, and we can get the cpu number by
> >> reading from the TP register + offsetof(struct thread_info, cpu).
> >>
> >> Once we have the cpu number in a register we read the offset for that
> >> cpu from address: &__per_cpu_offset + cpu_number << 3. Then we add this
> >> offset to the destination register.
> >>
> >> To measure the improvement from this change, the benchmark in [1] was
> >> used on Qemu:
> >>
> >> Before:
> >> glob-arr-inc   :    1.127 ± 0.013M/s
> >> arr-inc        :    1.121 ± 0.004M/s
> >> hash-inc       :    0.681 ± 0.052M/s
> >>
> >> After:
> >> glob-arr-inc   :    1.138 ± 0.011M/s
> >> arr-inc        :    1.366 ± 0.006M/s
> >> hash-inc       :    0.676 ± 0.001M/s
> >>
> >> [1] https://github.com/anakryiko/linux/commit/8dec900975ef
> >>
> >> Signed-off-by: Puranjay Mohan <puranjay@...nel.org>
> >> ---
> >>  arch/riscv/net/bpf_jit_comp64.c | 24 ++++++++++++++++++++++++
> >>  1 file changed, 24 insertions(+)
> >>
> >> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
> >> index 15e482f2c657..99d7006f1420 100644
> >> --- a/arch/riscv/net/bpf_jit_comp64.c
> >> +++ b/arch/riscv/net/bpf_jit_comp64.c
> >> @@ -12,6 +12,7 @@
> >>  #include <linux/stop_machine.h>
> >>  #include <asm/patch.h>
> >>  #include <asm/cfi.h>
> >> +#include <asm/percpu.h>
> >>  #include "bpf_jit.h"
> >>
> >>  #define RV_FENTRY_NINSNS 2
> >> @@ -1089,6 +1090,24 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
> >>                         emit_or(RV_REG_T1, rd, RV_REG_T1, ctx);
> >>                         emit_mv(rd, RV_REG_T1, ctx);
> >>                         break;
> >> +               } else if (insn_is_mov_percpu_addr(insn)) {
> >> +                       if (rd != rs)
> >> +                               emit_mv(rd, rs, ctx);
>
> No biggie, but you did not fold this check into emit_mv().
>
> >> +#ifdef CONFIG_SMP
> >> +                               /* Load current CPU number in T1 */
> >> +                               emit_ld(RV_REG_T1, offsetof(struct thread_info, cpu),
> >> +                                       RV_REG_TP, ctx);
> >> +                               /* << 3 because offsets are 8 bytes */
> >> +                               emit_slli(RV_REG_T1, RV_REG_T1, 3, ctx);
> >> +                               /* Load address of __per_cpu_offset array in T2 */
> >> +                               emit_addr(RV_REG_T2, (u64)&__per_cpu_offset, extra_pass, ctx);
> >> +                               /* Add offset of current CPU to  __per_cpu_offset */
> >> +                               emit_add(RV_REG_T1, RV_REG_T2, RV_REG_T1, ctx);
> >> +                               /* Load __per_cpu_offset[cpu] in T1 */
> >> +                               emit_ld(RV_REG_T1, 0, RV_REG_T1, ctx);
> >> +                               /* Add the offset to Rd */
> >> +                               emit_add(rd, rd, RV_REG_T1, ctx);
> >
> > is this the right level of code indentation?
>
> Looks wrong.
>
> When the indent is fixed, feel free to add:
>
> Acked-by: Björn Töpel <bjorn@...nel.org>

I fixed the indent and sent it as part of:
https://lore.kernel.org/all/20240502151854.9810-1-puranjay@kernel.org/

Also, for the emit_mv() thing, I wanted to verify if we are using that
somewhere for zero-extension or something.
So, I thought I would send a separate patch for it.

Thanks,
Puranjay