linux-kernel - Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

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Date: Thu, 2 May 2024 17:37:00 +0100
From: Conor Dooley <conor@...nel.org>
To: Yunhui Cui <cuiyunhui@...edance.com>
Cc: rafael@...nel.org, lenb@...nel.org, linux-acpi@...r.kernel.org,
	linux-kernel@...r.kernel.org, paul.walmsley@...ive.com,
	palmer@...belt.com, aou@...s.berkeley.edu,
	linux-riscv@...ts.infradead.org, bhelgaas@...gle.com,
	james.morse@....com, jhugo@...eaurora.org, jeremy.linton@....com,
	john.garry@...wei.com, Jonathan.Cameron@...wei.com,
	pierre.gondois@....com, sudeep.holla@....com, tiantao6@...wei.com
Subject: Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level
 and type from ACPI PPTT

On Thu, Apr 18, 2024 at 11:43:29AM +0800, Yunhui Cui wrote:
> Before cacheinfo can be built correctly, we need to initialize level
> and type. Since RSIC-V currently does not have a register group that
> describes cache-related attributes like ARM64, we cannot obtain them
> directly, so now we obtain cache leaves from the ACPI PPTT table
> (acpi_get_cache_info()) and set the cache type through split_levels.
> 
> Suggested-by: Jeremy Linton <jeremy.linton@....com>
> Suggested-by: Sudeep Holla <sudeep.holla@....com>
: Signed-off-by: Yunhui Cui <cuiyunhui@...edance.com>

I'm not an ACPI head, so whether or not the table is valid on RISC-V or
w/e I do not know, but the code here looks sane to me, so
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>

Cheers,
Conor.

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