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Date: Thu, 2 May 2024 18:53:28 +0200
From: Alexandre Mergnat <amergnat@...libre.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
chunkuang.hu@...nel.org
Cc: robh@...nel.org, krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
p.zabel@...gutronix.de, airlied@...il.com, daniel@...ll.ch,
maarten.lankhorst@...ux.intel.com, mripard@...nel.org, tzimmermann@...e.de,
matthias.bgg@...il.com, shawn.sung@...iatek.com, yu-chang.lee@...iatek.com,
ck.hu@...iatek.com, jitao.shi@...iatek.com, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org,
linux-mediatek@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org,
wenst@...omium.org, kernel@...labora.com
Subject: Re: [PATCH v2 0/3] drm/mediatek: Add support for OF graphs
On 30/04/2024 13:33, AngeloGioacchino Del Regno wrote:
> Il 30/04/24 12:17, Alexandre Mergnat ha scritto:
>> Hi Angelo,
>>
>> On 09/04/2024 14:02, AngeloGioacchino Del Regno wrote:
>>> This series was tested on MT8195 Cherry Tomato and on MT8395 Radxa
>>> NIO-12L with both hardcoded paths, OF graph support and partially
>>> hardcoded paths (meaning main display through OF graph and external
>>> display hardcoded, because of OVL_ADAPTOR).
>>
>> Is that make sense for you to add the DTS changes of these boards into this serie ?
>> I asked because, IMHO, that could help to understand the serie.
>>
>
> Yes and no... but I imagine that you're asking this because you're trying to
> prepare something with a different SoC+board(s) combination :-)
>
> In that case, I'm preventively sorry because what follows here is not 100%
> perfectly tidy yet as I didn't mean to send the devicetree commits upstream
> before this series got picked....
>
> ... but there you go - I'm sure that you won't mind and that the example will
> be more than good enough for you.
>
> Please note that one of the reasons why I didn't want to add this to the series
> is that the following changes show only a mere 50% of the reasons why we want OF
> graph support on mediatek-drm (but mainly, it's because I didn't have time to
> actually rebase etc :-P )
Thanks for the explanations and examples.
Unfortunately, I have 2 display but only one is working (the main: DSI0) when I use the dts method.
I've probably missed something but I don't know what.
In my "mmsys" node, if I swap display (the ext endpoint with the main endpoint), the DPI0 is
working, but not the DSI0. I conclude my both paths are good.
Then, I've put some trace into "mtk_drm_of_ddp_path_build" to check if it parse the two endpoint of
the node. Both are parsed, but "of_ep.port" is always = 0. According to "of_graph_parse_endpoint"
function, "port" is the value of the parent "reg", whereas "id" is the value of the endpoint "reg".
So I replaced "of_ep.port" by "of_ep.id". Now I've of_ep.id = 0 for main and of_ep.id = 1 for EXT.
Now I've the good CRTC path, I get this error:
mediatek-drm mediatek-drm.1.auto: Invalid display hw pipeline. Last component: 54 (ret=-2)
mediatek-drm mediatek-drm.1.auto: probe with driver mediatek-drm failed with error -22
After quick look, the "cpath" into "mtk_drm_of_ddp_path_build_one" (or deeper functions) seems not
be used as it should, due to the previous "of_ep.port" => "of_ep.id" change of course.
But I probably have to fix "of_ep.port" because I've mis-coded something. Just in case, I share you
my diff:
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index 1aa3426f561b..f660481d3fe8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -109,15 +109,51 @@ vsys_lcm_reg: regulator-vsys-lcm {
};
};
+&cpu0 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&cpu1 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&cpu2 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&cpu3 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&dither0_out {
+ remote-endpoint = <&dsi0_in>;
+};
+
&dpi0 {
pinctrl-0 = <&dpi_default_pins>;
pinctrl-1 = <&dpi_idle_pins>;
pinctrl-names = "default", "sleep";
status = "okay";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- port {
- dpi_out: endpoint {
- remote-endpoint = <&it66121_in>;
+ port@0 {
+ reg = <0>;
+ dpi0_in: endpoint {
+ remote-endpoint = <&rdma1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpi0_out: endpoint {
+ remote-endpoint = <&it66121_in>;
+ };
};
};
};
@@ -137,36 +173,28 @@ panel@0 {
port {
panel_in: endpoint {
- remote-endpoint = <&dsi_out>;
+ remote-endpoint = <&dsi0_out>;
};
};
};
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- port {
- dsi_out: endpoint {
- remote-endpoint = <&panel_in>;
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dither0_out>;
+ };
};
- };
-};
-&cpu0 {
- proc-supply = <&mt6357_vproc_reg>;
- sram-supply = <&mt6357_vsram_proc_reg>;
-};
-
-&cpu1 {
- proc-supply = <&mt6357_vproc_reg>;
- sram-supply = <&mt6357_vsram_proc_reg>;
-};
-
-&cpu2 {
- proc-supply = <&mt6357_vproc_reg>;
- sram-supply = <&mt6357_vsram_proc_reg>;
-};
-
-&cpu3 {
- proc-supply = <&mt6357_vproc_reg>;
- sram-supply = <&mt6357_vsram_proc_reg>;
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
};
ðernet {
@@ -229,7 +257,7 @@ port@0 {
reg = <0>;
it66121_in: endpoint {
bus-width = <12>;
- remote-endpoint = <&dpi_out>;
+ remote-endpoint = <&dpi0_out>;
};
};
@@ -557,6 +585,10 @@ &pwm {
status = "okay";
};
+&rdma1_out {
+ remote-endpoint = <&dpi0_in>;
+};
+
&ssusb {
dr_mode = "otg";
maximum-speed = "high-speed";
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index d34519a33c90..dbb559959a9d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -762,6 +762,19 @@ mmsys: syscon@...00000 {
compatible = "mediatek,mt8365-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mmsys_main: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&ovl0_in>;
+ };
+ mmsys_ext: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&rdma1_in>;
+ };
+ };
};
mutex: mutex@...01000 {
@@ -801,6 +814,24 @@ ovl0: ovl@...0b000 {
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ ovl0_in: endpoint {
+ remote-endpoint = <&mmsys_main>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ovl0_out: endpoint {
+ remote-endpoint = <&rdma0_in>;
+ };
+ };
+ };
};
rdma0: rdma@...0d000 {
@@ -811,6 +842,24 @@ rdma0: rdma@...0d000 {
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
mediatek,rdma-fifo-size = <5120>;
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ rdma0_in: endpoint {
+ remote-endpoint = <&ovl0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ rdma0_out: endpoint {
+ remote-endpoint = <&color0_in>;
+ };
+ };
+ };
};
color0: color@...0f000 {
@@ -819,6 +868,24 @@ color0: color@...0f000 {
clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ color0_in: endpoint {
+ remote-endpoint = <&rdma0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ color0_out: endpoint {
+ remote-endpoint = <&ccorr0_in>;
+ };
+ };
+ };
};
ccorr0: ccorr@...10000 {
@@ -827,6 +894,24 @@ ccorr0: ccorr@...10000 {
clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ ccorr0_in: endpoint {
+ remote-endpoint = <&color0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ccorr0_out: endpoint {
+ remote-endpoint = <&aal0_in>;
+ };
+ };
+ };
};
aal0: aal@...11000 {
@@ -835,6 +920,24 @@ aal0: aal@...11000 {
clocks = <&mmsys CLK_MM_MM_DISP_AAL0>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ aal0_in: endpoint {
+ remote-endpoint = <&ccorr0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ aal0_out: endpoint {
+ remote-endpoint = <&gamma0_in>;
+ };
+ };
+ };
};
gamma0: gamma@...12000 {
@@ -843,6 +946,24 @@ gamma0: gamma@...12000 {
clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ gamma0_in: endpoint {
+ remote-endpoint = <&aal0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ gamma0_out: endpoint {
+ remote-endpoint = <&dither0_in>;
+ };
+ };
+ };
};
dither0: dither@...13000 {
@@ -851,6 +972,23 @@ dither0: dither@...13000 {
clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dither0_in: endpoint {
+ remote-endpoint = <&gamma0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dither0_out: endpoint {
+ };
+ };
+ };
};
dsi0: dsi@...14000 {
@@ -874,6 +1012,23 @@ rdma1: rdma@...16000 {
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
mediatek,rdma-fifo-size = <2048>;
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ rdma1_in: endpoint {
+ remote-endpoint = <&mmsys_ext>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ rdma1_out: endpoint {
+ };
+ };
+ };
};
dpi0: dpi@...18000 {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index dacf4eaa3457..5992b7865310 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -230,22 +230,6 @@ static const unsigned int mt8195_mtk_ddp_ext[] = {
DDP_COMPONENT_DP_INTF1,
};
-static const unsigned int mt8365_mtk_ddp_main[] = {
- DDP_COMPONENT_OVL0,
- DDP_COMPONENT_RDMA0,
- DDP_COMPONENT_COLOR0,
- DDP_COMPONENT_CCORR,
- DDP_COMPONENT_AAL0,
- DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER0,
- DDP_COMPONENT_DSI0,
-};
-
-static const unsigned int mt8365_mtk_ddp_ext[] = {
- DDP_COMPONENT_RDMA1,
- DDP_COMPONENT_DPI0,
-};
-
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -334,10 +318,6 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
};
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
- .main_path = mt8365_mtk_ddp_main,
- .main_len = ARRAY_SIZE(mt8365_mtk_ddp_main),
- .ext_path = mt8365_mtk_ddp_ext,
- .ext_len = ARRAY_SIZE(mt8365_mtk_ddp_ext),
.mmsys_dev_num = 1,
};
--
Regards,
Alexandre
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