linux-kernel - Re: [PATCH v2 2/5] mips: bmips: rework and cache CBR addr handling

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Message-ID: <ff3df04e-300d-4ee1-840f-09bbd15ac3d5@broadcom.com>
Date: Fri, 3 May 2024 14:23:47 -0700
From: Florian Fainelli <florian.fainelli@...adcom.com>
To: Christian Marangi <ansuelsmth@...il.com>,
 Hauke Mehrtens <hauke@...ke-m.de>, Rafał Miłecki
 <zajec5@...il.com>, Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
 Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>,
 Broadcom internal kernel review list
 <bcm-kernel-feedback-list@...adcom.com>,
 Álvaro Fernández Rojas <noltari@...il.com>,
 linux-mips@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, Daniel González Cabanelas
 <dgcbueu@...il.com>
Subject: Re: [PATCH v2 2/5] mips: bmips: rework and cache CBR addr handling

On 5/3/24 14:20, Christian Marangi wrote:
> Rework the handling of the CBR address and cache it. This address
> doesn't change and can be cached instead of reading the register every
> time.
> 
> This is in preparation of permitting to tweak the CBR address in DT with
> broken SoC or bootloader.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@...il.com>

Acked-by: Florian Fainelli <florian.fainelli@...adcom.com>
-- 
Florian


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