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Message-ID: <d613aa4d-8c87-4735-8209-00510d5097fb@kwiboo.se>
Date: Fri, 3 May 2024 23:46:06 +0200
From: Jonas Karlman <jonas@...boo.se>
To: Chukun Pan <amadeus@....edu.cn>
Cc: Heiko Stuebner <heiko@...ech.de>, Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Rob Herring <robh@...nel.org>,
linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Radxa ROCK 3C
Hi Chukun,
On 2024-04-28 14:36, Chukun Pan wrote:
> The Radxa ROCK 3C is a development board with the
> Rockchip RK3566 SoC. It has the following features:
>
> - 1/2/4GB LPDDR4
> - 1x HDMI Type A
> - 1x PCIE 2.0 slot
> - 1x FAN connector
> - 3.5mm jack with mic
> - 1GbE RTL8211F Ethernet
> - 1x USB 3.0, 3x USB 2.0
> - 40-pin expansion header
> - MicroSD card/eMMC socket
> - 16MB SPI NOR (gd25lq128d)
> - AP6256 or AIC8800 WiFi/BT
>
> Signed-off-by: Chukun Pan <amadeus@....edu.cn>
> ---
> arch/arm64/boot/dts/rockchip/Makefile | 1 +
> .../boot/dts/rockchip/rk3566-rock-3c.dts | 750 ++++++++++++++++++
> 2 files changed, 751 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
>
[snip]
> +
> +&i2c0 {
> + status = "okay";
> +
> + vdd_cpu: regulator@1c {
> + compatible = "tcs,tcs4525";
> + reg = <0x1c>;
> + fcs,suspend-voltage-selector = <1>;
> + regulator-name = "vdd_cpu";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1150000>;
> + regulator-ramp-delay = <2300>;
> + vin-supply = <&vcc5v0_sys>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + rk809: pmic@20 {
> + compatible = "rockchip,rk809";
> + reg = <0x20>;
[snip]
> + codec {
> + mic-in-differential;
This should be rockchip,mic-in-differential or removed.
> + };
> + };
> +
> + eeprom: eeprom@50 {
> + compatible = "belling,bl24c16a", "atmel,24c16";
> + reg = <0x50>;
> + pagesize = <16>;
> + };
> +};
> +
[snip]
> +
> +&sdmmc0 {
> + bus-width = <4>;
> + cap-sd-highspeed;
> + disable-wp;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
> + sd-uhs-sdr50;
Do you have any references to issues related to why sd-uhs-sdr104 is not
used here?
My testing shows that io-domain is getting notified and correctly
configured during boot. And card seem to be working correctly.
[ 2.162780] mmc_host mmc1: Bus speed (slot 0) = 375000Hz (slot req 400000Hz, actual 375000HZ div = 0)
[ 2.229408] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000
[ 2.230042] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000 done
[ 2.231493] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 1800000
[ 2.232121] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 1800000 done
[ 2.257294] mmc_host mmc1: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0)
[ 2.269482] dwmmc_rockchip fe2b0000.mmc: Successfully tuned phase to 254
[ 2.270098] mmc1: new ultra high speed SDR104 SDXC card at address aaaa
[ 2.271533] mmcblk1: mmc1:aaaa SD64G 59.5 GiB
[ 2.277357] mmcblk1: p1
Also when the card is later removed/re-inserted:
[ 80.181598] mmc1: card aaaa removed
[ 83.836785] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000
[ 83.837611] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000 done
[ 83.839263] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000
[ 83.839952] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000 done
[ 83.855358] mmc_host mmc1: Bus speed (slot 0) = 375000Hz (slot req 400000Hz, actual 375000HZ div = 0)
[ 84.153827] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000
[ 84.154524] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000 done
[ 84.156149] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 1800000
[ 84.156838] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 1800000 done
[ 84.183932] mmc_host mmc1: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0)
[ 84.202888] dwmmc_rockchip fe2b0000.mmc: Successfully tuned phase to 257
[ 84.203574] mmc1: new ultra high speed SDR104 SDXC card at address aaaa
[ 84.205537] mmcblk1: mmc1:aaaa SD64G 59.5 GiB
[ 84.211434] mmcblk1: p1
sd-uhs-ddr50 should also work based on my testing.
Regards,
Jonas
> + vmmc-supply = <&vcc3v3_sys>;
> + vqmmc-supply = <&vccio_sd>;
> + status = "okay";
> +};
> +
[snip]
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