[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <202405031322.8UuTAWrf-lkp@intel.com>
Date: Fri, 3 May 2024 13:37:50 +0800
From: kernel test robot <lkp@...el.com>
To: Prajna Rajendra Kumar <prajna.rajendrakumar@...rochip.com>,
Mark Brown <broonie@...nel.org>
Cc: oe-kbuild-all@...ts.linux.dev, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk@...nel.org>,
linux-riscv@...ts.infradead.org, linux-spi@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Conor Dooley <conor.dooley@...rochip.com>,
Daire McNamara <daire.mcnamara@...rochip.com>,
valentina.fernandezalanis@...rochip.com,
Prajna Rajendra Kumar <prajna.rajendrakumar@...rochip.com>
Subject: Re: [PATCH 1/3] spi: spi-microchip-core: Add support for GPIO based
CS
Hi Prajna,
kernel test robot noticed the following build warnings:
[auto build test WARNING on broonie-spi/for-next]
[also build test WARNING on robh/for-next krzk-dt/for-next linus/master v6.9-rc6 next-20240502]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Prajna-Rajendra-Kumar/spi-spi-microchip-core-Add-support-for-GPIO-based-CS/20240502-223714
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
patch link: https://lore.kernel.org/r/20240502143410.12629-2-prajna.rajendrakumar%40microchip.com
patch subject: [PATCH 1/3] spi: spi-microchip-core: Add support for GPIO based CS
config: sh-allmodconfig (https://download.01.org/0day-ci/archive/20240503/202405031322.8UuTAWrf-lkp@intel.com/config)
compiler: sh4-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240503/202405031322.8UuTAWrf-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202405031322.8UuTAWrf-lkp@intel.com/
All warnings (new ones prefixed by >>):
drivers/spi/spi-microchip-core.c: In function 'mchp_corespi_setup':
>> drivers/spi/spi-microchip-core.c:261:13: warning: the comparison will always evaluate as 'true' for the address of 'cs_gpiod' will never be NULL [-Waddress]
261 | if (spi->cs_gpiod)
| ^~~
In file included from drivers/spi/spi-microchip-core.c:21:
include/linux/spi/spi.h:219:34: note: 'cs_gpiod' declared here
219 | struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /* Chip select gpio desc */
| ^~~~~~~~
vim +261 drivers/spi/spi-microchip-core.c
255
256 static int mchp_corespi_setup(struct spi_device *spi)
257 {
258 struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);
259 u32 reg;
260
> 261 if (spi->cs_gpiod)
262 return 0;
263
264 /*
265 * Active high targets need to be specifically set to their inactive
266 * states during probe by adding them to the "control group" & thus
267 * driving their select line low.
268 */
269 if (spi->mode & SPI_CS_HIGH) {
270 reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);
271 reg |= BIT(spi_get_chipselect(spi, 0));
272 mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg);
273 }
274 return 0;
275 }
276
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Powered by blists - more mailing lists