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Date: Fri, 3 May 2024 10:46:48 +0200
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Jerome Brunet <jbrunet@...libre.com>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>
Cc: Kevin Hilman <khilman@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
dri-devel@...ts.freedesktop.org, linux-amlogic@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] drm/meson: dw-hdmi: add bandgap setting for g12
On 26/04/2024 18:02, Jerome Brunet wrote:
> When no mode is set, the utility pin appears to be grounded. No signal
> is getting through.
>
> This is problematic because ARC and eARC use this line and may do so even
> if no display mode is set.
>
> This change enable the bandgap setting on g12 chip, which fix the problem
> with the utility pin. This is done by restoring init values on PHY init and
> disable.
>
> Fixes: 3b7c1237a72a ("drm/meson: Add G12A support for the DW-HDMI Glue")
> Signed-off-by: Jerome Brunet <jbrunet@...libre.com>
> ---
> drivers/gpu/drm/meson/meson_dw_hdmi.c | 43 ++++++++++++++++-----------
> 1 file changed, 26 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
> index a83d93078537..5565f7777529 100644
> --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
> +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
> @@ -106,6 +106,8 @@
> #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */
> #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */
> #define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */
> +#define PHY_CNTL1_INIT 0x03900000
> +#define PHY_INVERT BIT(17)
> #define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */
> #define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */
> #define HHI_HDMI_PHY_CNTL4 0x3b0 /* 0xec */
> @@ -130,6 +132,8 @@ struct meson_dw_hdmi_data {
> unsigned int addr);
> void (*dwc_write)(struct meson_dw_hdmi *dw_hdmi,
> unsigned int addr, unsigned int data);
> + u32 cntl0_init;
> + u32 cntl1_init;
> };
>
> struct meson_dw_hdmi {
> @@ -458,7 +462,9 @@ static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi,
>
> DRM_DEBUG_DRIVER("\n");
>
> - regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
> + /* Fallback to init mode */
> + regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, dw_hdmi->data->cntl1_init);
> + regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, dw_hdmi->data->cntl0_init);
> }
>
> static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi,
> @@ -576,11 +582,22 @@ static const struct regmap_config meson_dw_hdmi_regmap_config = {
> .fast_io = true,
> };
>
> -static const struct meson_dw_hdmi_data meson_dw_hdmi_gx_data = {
> +static const struct meson_dw_hdmi_data meson_dw_hdmi_gxbb_data = {
> .top_read = dw_hdmi_top_read,
> .top_write = dw_hdmi_top_write,
> .dwc_read = dw_hdmi_dwc_read,
> .dwc_write = dw_hdmi_dwc_write,
> + .cntl0_init = 0x0,
> + .cntl1_init = PHY_CNTL1_INIT | PHY_INVERT,
> +};
> +
> +static const struct meson_dw_hdmi_data meson_dw_hdmi_gxl_data = {
> + .top_read = dw_hdmi_top_read,
> + .top_write = dw_hdmi_top_write,
> + .dwc_read = dw_hdmi_dwc_read,
> + .dwc_write = dw_hdmi_dwc_write,
> + .cntl0_init = 0x0,
> + .cntl1_init = PHY_CNTL1_INIT,
> };
>
> static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = {
> @@ -588,6 +605,8 @@ static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = {
> .top_write = dw_hdmi_g12a_top_write,
> .dwc_read = dw_hdmi_g12a_dwc_read,
> .dwc_write = dw_hdmi_g12a_dwc_write,
> + .cntl0_init = 0x000b4242, /* Bandgap */
> + .cntl1_init = PHY_CNTL1_INIT,
> };
>
> static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi)
> @@ -626,18 +645,8 @@ static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi)
> meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
>
> /* Setup PHY */
> - regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
> - 0xffff << 16, 0x0390 << 16);
> -
> - /* BIT_INVERT */
> - if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
> - dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||
> - dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))
> - regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
> - BIT(17), 0);
> - else
> - regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
> - BIT(17), BIT(17));
> + regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, meson_dw_hdmi->data->cntl1_init);
> + regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, meson_dw_hdmi->data->cntl0_init);
>
> /* Enable HDMI-TX Interrupt */
> meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
> @@ -848,11 +857,11 @@ static const struct dev_pm_ops meson_dw_hdmi_pm_ops = {
>
> static const struct of_device_id meson_dw_hdmi_of_table[] = {
> { .compatible = "amlogic,meson-gxbb-dw-hdmi",
> - .data = &meson_dw_hdmi_gx_data },
> + .data = &meson_dw_hdmi_gxbb_data },
> { .compatible = "amlogic,meson-gxl-dw-hdmi",
> - .data = &meson_dw_hdmi_gx_data },
> + .data = &meson_dw_hdmi_gxl_data },
> { .compatible = "amlogic,meson-gxm-dw-hdmi",
> - .data = &meson_dw_hdmi_gx_data },
> + .data = &meson_dw_hdmi_gxl_data },
> { .compatible = "amlogic,meson-g12a-dw-hdmi",
> .data = &meson_dw_hdmi_g12a_data },
> { }
Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>
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