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Date: Fri, 3 May 2024 11:34:22 -0400
From: Sean Anderson <sean.anderson@...ux.dev>
To: Michal Simek <michal.simek@....com>,
linux-arm-kernel@...ts.infradead.org
Cc: Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org,
Rob Herring <robh@...nel.org>,
Sean Anderson <sean.anderson@...ux.dev>
Subject: [PATCH] arm64: zynqmp: Add coresight cpu debug support
Add coresight debug support to the device tree. This can be useful when
panicking, especially when a core is hung in EL3.
Signed-off-by: Sean Anderson <sean.anderson@...ux.dev>
---
.../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 16 +++++++++++
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 28 +++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index dd4569e7bd95..60d1b1acf9a0 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -70,6 +70,22 @@ &cpu0 {
clocks = <&zynqmp_clk ACPU>;
};
+&cpu0_debug {
+ clocks = <&zynqmp_clk DBF_FPD>;
+};
+
+&cpu1_debug {
+ clocks = <&zynqmp_clk DBF_FPD>;
+};
+
+&cpu2_debug {
+ clocks = <&zynqmp_clk DBF_FPD>;
+};
+
+&cpu3_debug {
+ clocks = <&zynqmp_clk DBF_FPD>;
+};
+
&fpd_dma_chan1 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 25d20d803230..ec8d5d19ac1c 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -330,6 +330,34 @@ pmu@...0 {
};
};
+ cpu0_debug: debug@...10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfec10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ };
+
+ cpu1_debug: debug@...10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfed10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+ };
+
+ cpu2_debug: debug@...10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfee10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+ };
+
+ cpu3_debug: debug@...10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfef10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+ };
+
/* GDMA */
fpd_dma_chan1: dma-controller@...00000 {
status = "disabled";
--
2.35.1.1320.gc452695387.dirty
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