linux-kernel - Re: [PATCH v4 7/7] iommu/riscv: Paging domain support

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Date: Sat, 4 May 2024 10:03:59 +0800
From: Baolu Lu <baolu.lu@...ux.intel.com>
To: Tomasz Jeznach <tjeznach@...osinc.com>, Joerg Roedel <joro@...tes.org>,
 Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>,
 Paul Walmsley <paul.walmsley@...ive.com>
Cc: baolu.lu@...ux.intel.com, Palmer Dabbelt <palmer@...belt.com>,
 Albert Ou <aou@...s.berkeley.edu>, Anup Patel <apatel@...tanamicro.com>,
 Sunil V L <sunilvl@...tanamicro.com>, Nick Kossifidis <mick@....forth.gr>,
 Sebastien Boeuf <seb@...osinc.com>, Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, devicetree@...r.kernel.org, iommu@...ts.linux.dev,
 linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
 linux@...osinc.com
Subject: Re: [PATCH v4 7/7] iommu/riscv: Paging domain support

On 5/4/24 12:12 AM, Tomasz Jeznach wrote:
> Introduce first-stage address translation support.
> 
> Page table configured by the IOMMU driver will use the highest mode
> implemented by the hardware, unless not known at the domain allocation
> time falling back to the CPU’s MMU page mode.
> 
> This change introduces IOTINVAL.VMA command, required to invalidate
> any cached IOATC entries after mapping is updated and/or removed from
> the paging domain.  Invalidations for the non-leaf page entries use
> IOTINVAL for all addresses assigned to the protection domain for
> hardware not supporting more granular non-leaf page table cache
> invalidations.
> 
> Signed-off-by: Tomasz Jeznach<tjeznach@...osinc.com>

Reviewed-by: Lu Baolu <baolu.lu@...ux.intel.com>

Best regards,
baolu