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Message-Id: <D12H4GDJJEUF.1Y91H9RMUIX20@kernel.org>
Date: Mon, 06 May 2024 12:02:16 +0200
From: "Michael Walle" <mwalle@...nel.org>
To: "AngeloGioacchino Del Regno" <angelogioacchino.delregno@...labora.com>,
"Alexandre Mergnat" <amergnat@...libre.com>, <chunkuang.hu@...nel.org>
Cc: <robh@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<conor+dt@...nel.org>, <p.zabel@...gutronix.de>, <airlied@...il.com>,
<daniel@...ll.ch>, <maarten.lankhorst@...ux.intel.com>,
<mripard@...nel.org>, <tzimmermann@...e.de>, <matthias.bgg@...il.com>,
<shawn.sung@...iatek.com>, <yu-chang.lee@...iatek.com>,
<ck.hu@...iatek.com>, <jitao.shi@...iatek.com>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<dri-devel@...ts.freedesktop.org>, <linux-mediatek@...ts.infradead.org>,
<linux-arm-kernel@...ts.infradead.org>, <wenst@...omium.org>,
<kernel@...labora.com>
Subject: Re: [PATCH v2 0/3] drm/mediatek: Add support for OF graphs
Hi Angelo,
On Tue Apr 30, 2024 at 1:33 PM CEST, AngeloGioacchino Del Regno wrote:
> >> This series was tested on MT8195 Cherry Tomato and on MT8395 Radxa
> >> NIO-12L with both hardcoded paths, OF graph support and partially
> >> hardcoded paths (meaning main display through OF graph and external
> >> display hardcoded, because of OVL_ADAPTOR).
> >
> > Is that make sense for you to add the DTS changes of these boards into this serie ?
> > I asked because, IMHO, that could help to understand the serie.
> >
>
> Yes and no... but I imagine that you're asking this because you're trying to
> prepare something with a different SoC+board(s) combination :-)
>
> In that case, I'm preventively sorry because what follows here is not 100%
> perfectly tidy yet as I didn't mean to send the devicetree commits upstream
> before this series got picked....
>
> ... but there you go - I'm sure that you won't mind and that the example will
> be more than good enough for you.
I've tested this series with the DSI0 output and it works. Nice! No
need for my DSI0 patch for the MT8395 anymore.
But I can't get it to work with the DisplayPort output, that is the
dp_intf1/dp_tx interface. I don' know how the pipeline have to look
like. The functional spec seems to be ambiguous on this. The text
seem to refer to the second vdosys but there is also a diagram where
you can use the first vdosys and dsc0. If you have any pointers for
me, I'm all ears :)
-michael
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