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Date: Mon, 6 May 2024 13:09:02 +0100
From: Conor Dooley <conor@...nel.org>
To: Leyfoon Tan <leyfoon.tan@...rfivetech.com>
Cc: Linus Walleij <linus.walleij@...aro.org>,
	Yuklin Soo <yuklin.soo@...rfivetech.com>,
	Bartosz Golaszewski <bartosz.golaszewski@...aro.org>,
	Hal Feng <hal.feng@...rfivetech.com>,
	Emil Renner Berthing <kernel@...il.dk>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Drew Fustini <drew@...gleboard.org>,
	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>
Subject: Re: [RFC PATCH v3 0/7] Add Pinctrl driver for Starfive JH8100 SoC

On Mon, May 06, 2024 at 07:31:19AM +0000, Leyfoon Tan wrote:
> 
> 
> > -----Original Message-----
> > From: Linus Walleij <linus.walleij@...aro.org>
> > Sent: Monday, May 6, 2024 2:35 PM
> > To: Yuklin Soo <yuklin.soo@...rfivetech.com>
> > Cc: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>; Hal Feng
> > <hal.feng@...rfivetech.com>; Leyfoon Tan <leyfoon.tan@...rfivetech.com>;
> > Jianlong Huang <jianlong.huang@...rfivetech.com>; Emil Renner Berthing
> > <kernel@...il.dk>; Rob Herring <robh@...nel.org>; Krzysztof Kozlowski
> > <krzysztof.kozlowski+dt@...aro.org>; Conor Dooley <conor+dt@...nel.org>;
> > Drew Fustini <drew@...gleboard.org>; linux-gpio@...r.kernel.org; linux-
> > kernel@...r.kernel.org; devicetree@...r.kernel.org; linux-
> > riscv@...ts.infradead.org; Paul Walmsley <paul.walmsley@...ive.com>; Palmer
> > Dabbelt <palmer@...belt.com>; Albert Ou <aou@...s.berkeley.edu>
> > Subject: Re: [RFC PATCH v3 0/7] Add Pinctrl driver for Starfive JH8100 SoC
> > 
> > On Fri, May 3, 2024 at 1:14 PM Alex Soo <yuklin.soo@...rfivetech.com>
> > wrote:
> > 
> > > Starfive JH8100 SoC consists of 4 pinctrl domains - sys_east,
> > > sys_west, sys_gmac, and aon. This patch series adds pinctrl drivers
> > > for these 4 pinctrl domains and this patch series is depending on the
> > > JH8100 base patch series in [1] and [2].
> > > The relevant dt-binding documentation for each pinctrl domain has been
> > > updated accordingly.
> > >
> > > [1]
> > > https://lore.kernel.org/lkml/20231201121410.95298-1-jeeheng.sia@starfi
> > > vetech.com/ [2]
> > > https://lore.kernel.org/lkml/20231206115000.295825-1-
> > jeeheng.sia@...rf
> > > ivetech.com/
> > 
> > v3 is starting to look very nice, why is this patch set still in "RFC"?
> > 
> > I would like some proper review from the StarFive maintainers at this point so
> > we can get it finished.
> > 
> > Yours,
> > Linus Walleij
> 
> Hi Linus
> 
> Thanks for reviewing the patches.
> 
> There is a discussion in another thread about the JH8100 SoC being validated on FPGA/Emulation only now.  The suggestion is to send the patches as "RFC" before the real silicon availability.
> 
> https://patchew.org/linux/20231201121410.95298-1-jeeheng.sia@starfivetech.com/20231201121410.95298-3-jeeheng.sia@starfivetech.com/

I know I said "drivers" in that mail you link to, but I was mostly
concerned about binding headers etc, of which I think there are actually
none here, so see my reply to this thread a few days ago:
https://lore.kernel.org/all/20240503-undress-mantra-e5e46b2f6360@spud/

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