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Message-Id: <20240506-tc358775-fix-powerup-v1-6-545dcf00b8dd@kernel.org>
Date: Mon, 06 May 2024 15:34:35 +0200
From: Michael Walle <mwalle@...nel.org>
To: Andrzej Hajda <andrzej.hajda@...el.com>,
Neil Armstrong <neil.armstrong@...aro.org>, Robert Foss <rfoss@...nel.org>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
Jonas Karlman <jonas@...boo.se>, Jernej Skrabec <jernej.skrabec@...il.com>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>,
Chun-Kuang Hu <chunkuang.hu@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
Sam Ravnborg <sam@...nborg.org>, Vinay Simha BN <simhavcs@...il.com>,
Tony Lindgren <tony@...mide.com>
Cc: Daniel Semkowicz <dse@...umatec.com>, dri-devel@...ts.freedesktop.org,
linux-kernel@...r.kernel.org, linux-mediatek@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, Michael Walle <mwalle@...nel.org>
Subject: [PATCH 06/20] drm/bridge: tc358775: redefine LV_MX()
Drop the FLD_VAL macro, just use bit shifts. This is a preparation patch
to switch to regmap and to remove the FLD_VAL().
While at it, reformat the LV_x enum.
Signed-off-by: Michael Walle <mwalle@...nel.org>
---
drivers/gpu/drm/bridge/tc358775.c | 36 ++++++------------------------------
1 file changed, 6 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358775.c b/drivers/gpu/drm/bridge/tc358775.c
index 720c0d63fd6a..7ae86e8d4c72 100644
--- a/drivers/gpu/drm/bridge/tc358775.c
+++ b/drivers/gpu/drm/bridge/tc358775.c
@@ -124,39 +124,15 @@
#define LV_MX1619 0x0490 /* Bit 16 to 19 */
#define LV_MX2023 0x0494 /* Bit 20 to 23 */
#define LV_MX2427 0x0498 /* Bit 24 to 27 */
-#define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
- FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24))
+#define LV_MX(b0, b1, b2, b3) \
+ (((b3) << 24) | ((b2) << 16) | ((b1) << 8) | (b0))
/* Input bit numbers used in mux registers */
enum {
- LVI_R0,
- LVI_R1,
- LVI_R2,
- LVI_R3,
- LVI_R4,
- LVI_R5,
- LVI_R6,
- LVI_R7,
- LVI_G0,
- LVI_G1,
- LVI_G2,
- LVI_G3,
- LVI_G4,
- LVI_G5,
- LVI_G6,
- LVI_G7,
- LVI_B0,
- LVI_B1,
- LVI_B2,
- LVI_B3,
- LVI_B4,
- LVI_B5,
- LVI_B6,
- LVI_B7,
- LVI_HS,
- LVI_VS,
- LVI_DE,
- LVI_L0
+ LVI_R0, LVI_R1, LVI_R2, LVI_R3, LVI_R4, LVI_R5, LVI_R6, LVI_R7,
+ LVI_G0, LVI_G1, LVI_G2, LVI_G3, LVI_G4, LVI_G5, LVI_G6, LVI_G7,
+ LVI_B0, LVI_B1, LVI_B2, LVI_B3, LVI_B4, LVI_B5, LVI_B6, LVI_B7,
+ LVI_HS, LVI_VS, LVI_DE, LVI_L0
};
#define LVCFG 0x049C /* LVDS Configuration */
--
2.39.2
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