| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20240506034627.66765-1-hal.feng@starfivetech.com> Date: Mon, 6 May 2024 11:46:27 +0800 From: Hal Feng <hal.feng@...rfivetech.com> To: Palmer Dabbelt <palmer@...belt.com>, Conor Dooley <conor.dooley@...rochip.com>, Emil Renner Berthing <emil.renner.berthing@...onical.com>, Paul Walmsley <paul.walmsley@...ive.com>, Albert Ou <aou@...s.berkeley.edu> Cc: Hal Feng <hal.feng@...rfivetech.com>, linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org Subject: [PATCH v2] riscv: defconfig: Enable StarFive JH7110 drivers Add support for StarFive JH7110 SoC and VisionFive 2 board. - Cache - Temperature sensor - PMIC (AXP15060) - Restart GPIO - RNG - I2C - SPI - Quad SPI - USB & USB 2.0 PHY & PCIe 2.0/USB 3.0 PHY - Audio (I2S / TDM / PWM-DAC) - MIPI-CSI2 RX & D-PHY RX Signed-off-by: Hal Feng <hal.feng@...rfivetech.com> --- As more drivers of StarFive JH7110 VisionFive 2 board are upstream, add support for them in riscv defconfig. Changes since v1: - Drop CONFIG_STAGING=y, CONFIG_STAGING_MEDIA=y, CONFIG_V4L_PLATFORM_DRIVERS=y, CONFIG_VIDEO_STARFIVE_CAMSS=m. - Change CONFIG_SENSORS_SFCTEMP as a module. - Drop CONFIG_CLK_STARFIVE_JH7110_*=y, because they are not critical to boot. - Update the commit message. History: v1: https://lore.kernel.org/all/20240403060902.42834-1-hal.feng@starfivetech.com/ --- arch/riscv/configs/defconfig | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index fc0ec2ee13bc..2c8e80b57edd 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -111,6 +111,7 @@ CONFIG_PCIE_XILINX=y CONFIG_PCIE_FU740=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +CONFIG_SIFIVE_CCACHE=y CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y @@ -154,24 +155,35 @@ CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_HW_RANDOM_JH7110=m +CONFIG_I2C=y CONFIG_I2C_CHARDEV=m +CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_MV64XXX=m CONFIG_I2C_RIIC=y CONFIG_SPI=y +CONFIG_SPI_CADENCE_QUADSPI=m +CONFIG_SPI_PL022=m CONFIG_SPI_RSPI=m CONFIG_SPI_SIFIVE=y CONFIG_SPI_SUN6I=y # CONFIG_PTP_1588_CLOCK is not set CONFIG_GPIO_SIFIVE=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_SENSORS_SFCTEMP=m CONFIG_CPU_THERMAL=y CONFIG_DEVFREQ_THERMAL=y CONFIG_RZG2L_THERMAL=y CONFIG_WATCHDOG=y CONFIG_SUNXI_WATCHDOG=y CONFIG_RENESAS_RZG2LWDT=y +CONFIG_MFD_AXP20X_I2C=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_AXP20X=y CONFIG_REGULATOR_GPIO=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_VIDEO_CADENCE_CSI2RX=m CONFIG_DRM=m CONFIG_DRM_RADEON=m CONFIG_DRM_NOUVEAU=m @@ -183,6 +195,10 @@ CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_SOC=y CONFIG_SND_SOC_RZ=m +CONFIG_SND_DESIGNWARE_I2S=m +CONFIG_SND_SOC_STARFIVE=m +CONFIG_SND_SOC_JH7110_PWMDAC=m +CONFIG_SND_SOC_JH7110_TDM=m CONFIG_SND_SOC_WM8978=m CONFIG_SND_SIMPLE_CARD=m CONFIG_USB=y @@ -196,6 +212,11 @@ CONFIG_USB_OHCI_HCD_PLATFORM=y CONFIG_USB_RENESAS_USBHS=m CONFIG_USB_STORAGE=y CONFIG_USB_UAS=y +CONFIG_USB_CDNS_SUPPORT=m +CONFIG_USB_CDNS3=m +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3_STARFIVE=m CONFIG_USB_MUSB_HDRC=m CONFIG_USB_MUSB_SUNXI=m CONFIG_NOP_USB_XCEIV=m @@ -244,6 +265,9 @@ CONFIG_RZG2L_ADC=m CONFIG_RESET_RZG2L_USBPHY_CTRL=y CONFIG_PHY_SUN4I_USB=m CONFIG_PHY_RCAR_GEN3_USB2=y +CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=m +CONFIG_PHY_STARFIVE_JH7110_PCIE=m +CONFIG_PHY_STARFIVE_JH7110_USB=m CONFIG_LIBNVDIMM=y CONFIG_NVMEM_SUNXI_SID=y CONFIG_EXT4_FS=y base-commit: dd5a440a31fae6e459c0d6271dddd62825505361 -- 2.43.2
Powered by blists - more mailing lists