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Message-ID: <ecd2b4c9-32d7-0436-a68b-17b94df85875@amd.com>
Date: Tue, 7 May 2024 09:38:44 +0530
From: Ravi Bangoria <ravi.bangoria@....com>
To: Tom Lendacky <thomas.lendacky@....com>, tglx@...utronix.de,
 mingo@...hat.com, bp@...en8.de, dave.hansen@...ux.intel.com,
 seanjc@...gle.com, pbonzini@...hat.com
Cc: hpa@...or.com, rmk+kernel@...linux.org.uk, peterz@...radead.org,
 james.morse@....com, lukas.bulwahn@...il.com, arjan@...ux.intel.com,
 j.granados@...sung.com, sibs@...natelecom.cn, nik.borisov@...e.com,
 michael.roth@....com, nikunj.dadhania@....com, babu.moger@....com,
 x86@...nel.org, kvm@...r.kernel.org, linux-kernel@...r.kernel.org,
 santosh.shukla@....com, ananth.narayan@....com, sandipan.das@....com,
 Ravi Bangoria <ravi.bangoria@....com>
Subject: Re: [PATCH 2/3] x86/bus_lock: Add support for AMD

>> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
>> index 39f316d50ae4..013d16479a24 100644
>> --- a/arch/x86/kernel/cpu/amd.c
>> +++ b/arch/x86/kernel/cpu/amd.c
>> @@ -1058,6 +1058,8 @@ static void init_amd(struct cpuinfo_x86 *c)
>>         /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */
>>       clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
>> +
>> +    bus_lock_init();
> 
> Can this call and the one in the intel.c be moved to common.c?

Makes sense. Will do it.

Thanks,
Ravi

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