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Message-ID: <20240507200640.GA955773-robh@kernel.org>
Date: Tue, 7 May 2024 15:06:40 -0500
From: Rob Herring <robh@...nel.org>
To: Sean Anderson <sean.anderson@...ux.dev>
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
linux-pci@...r.kernel.org, Michal Simek <michal.simek@....com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Thippeswamy Havalige <thippeswamy.havalige@....com>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
devicetree@...r.kernel.org
Subject: Re: [PATCH v2 1/7] dt-bindings: pci: xilinx-nwl: Add phys
On Mon, May 06, 2024 at 12:15:04PM -0400, Sean Anderson wrote:
> Add phys properties so Linux can power-on/configure the GTR
> transcievers.
>
> Signed-off-by: Sean Anderson <sean.anderson@...ux.dev>
> ---
>
> Changes in v2:
> - Remove phy-names
> - Add an example
>
> Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> index 426f90a47f35..693b29039a9b 100644
> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> @@ -61,6 +61,10 @@ properties:
> interrupt-map:
> maxItems: 4
>
> + phys:
> + minItems: 1
> + maxItems: 4
I assume this is 1 phy per lane, but don't make me assume and define it.
Rob
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