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Message-ID: <47908b0befd1e61c4024d6f871b97c9c11e4c0be.camel@mediatek.com>
Date: Tue, 7 May 2024 05:58:19 +0000
From: CK Hu (胡俊光) <ck.hu@...iatek.com>
To: Shawn Sung (宋孝謙) <Shawn.Sung@...iatek.com>,
"chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>,
"angelogioacchino.delregno@...labora.com"
<angelogioacchino.delregno@...labora.com>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>,
Bibby Hsieh (謝濟遠) <Bibby.Hsieh@...iatek.com>,
"jason-ch.chen@...iatek.corp-partner.google.com"
<jason-ch.chen@...iatek.corp-partner.google.com>,
Nancy Lin (林欣螢) <Nancy.Lin@...iatek.com>,
"daniel@...ll.ch" <daniel@...ll.ch>, "p.zabel@...gutronix.de"
<p.zabel@...gutronix.de>, "dri-devel@...ts.freedesktop.org"
<dri-devel@...ts.freedesktop.org>, "airlied@...il.com" <airlied@...il.com>,
"sean@...rly.run" <sean@...rly.run>, "matthias.bgg@...il.com"
<matthias.bgg@...il.com>, "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v7 01/18] soc: mediatek: Disable 9-bit alpha in ETHDR
Hi, Shawn:
On Thu, 2024-05-02 at 18:38 +0800, Shawn Sung wrote:
> From: Hsiao Chien Sung <shawn.sung@...iatek.com>
>
> ETHDR 9-bit alpha should be disabled by default,
> otherwise alpha blending will not work.
Please explain what is 9-bit alpha. Is ARGB8888 8-bit alpha? I don't
know there are 9-bit alpha. I would like to know which function would
be disabled when you disable 9-bit alpha.
Regards,
CK
>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@...labora.com>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@...iatek.com>
> ---
> drivers/soc/mediatek/mtk-mmsys.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index f370f4ec4b888..938240714e54c 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -236,6 +236,7 @@ void mtk_mmsys_mixer_in_config(struct device
> *dev, int idx, bool alpha_sel, u16
>
> mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx
> - 1) * 4, ~0,
> alpha << 16 | alpha, cmdq_pkt);
> + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(15 +
> idx), 0, cmdq_pkt);
> mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 +
> idx),
> alpha_sel << (19 + idx), cmdq_pkt);
> mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx -
> 1) * 4,
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