linux-kernel - Re: [PATCH v5 1/2] dt-bindings: mtd: amlogic,meson-nand: support fields for boot ROM code

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <771a35e4-db15-8c4d-29e9-7a984cb34abc@salutedevices.com>
Date: Tue, 7 May 2024 11:11:40 +0300
From: Arseniy Krasnov <avkrasnov@...utedevices.com>
To: Miquel Raynal <miquel.raynal@...tlin.com>
CC: Richard Weinberger <richard@....at>, Vignesh Raghavendra
	<vigneshr@...com>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, Neil
 Armstrong <neil.armstrong@...aro.org>, Kevin Hilman <khilman@...libre.com>,
	Jerome Brunet <jbrunet@...libre.com>, Martin Blumenstingl
	<martin.blumenstingl@...glemail.com>, <linux-mtd@...ts.infradead.org>,
	<devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
	<linux-amlogic@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
	<oxffffaa@...il.com>, <kernel@...rdevices.ru>
Subject: Re: [PATCH v5 1/2] dt-bindings: mtd: amlogic,meson-nand: support
 fields for boot ROM code



On 07.05.2024 11:05, Miquel Raynal wrote:
> Hi Arseniy,
> 
> avkrasnov@...utedevices.com wrote on Tue, 7 May 2024 10:35:51 +0300:
> 
>> On 07.05.2024 10:27, Miquel Raynal wrote:
>>> Hi Arseniy,
>>>
>>> avkrasnov@...utedevices.com wrote on Tue, 7 May 2024 09:53:06 +0300:
>>>   
>>>> On 06.05.2024 16:48, Miquel Raynal wrote:  
>>>>> Hi Arseniy,
>>>>>
>>>>> avkrasnov@...utedevices.com wrote on Tue, 16 Apr 2024 11:51:00 +0300:
>>>>>     
>>>>>> Boot ROM code on Meson requires that some pages on NAND must be written
>>>>>> in special mode: "short" ECC mode where each block is 384 bytes and
>>>>>> scrambling mode is on.    
>>>>>
>>>>> Ok
>>>>>     
>>>>>> Such pages located with the specified interval within specified offset.    
>>>>>
>>>>> I'm sorry I don't get that sentence.    
>>>>
>>>> Sorry, I mean this (let me draw :) ) :
>>>>
>>>> [ page 0 ][ page 1 ][ page 2 ][ page 3 ][ page 4 ][ page 5 ][ page 6 ][ page 7 ][ page 8 ][ page 9 ]
>>>>
>>>> For example, we have 10 pages starting from the beginning of the chip - this is "within specified offset",
>>>> e.g. offset is 10. BootROM on axg needs that (for example) every third page must be written in "special"
>>>> mode: scrambling is on and ECC is 384 bytes. Such pages are 0, 2, 4, 6, 8. E.g. "specified interval" will
>>>> be 3.  
>>>
>>> Shall be 2, no?  
>>
>> yes, starting from 0 - then 2. e.g.
>> if (!(page_num % 2))
>>     boot ROM need this page
>>
>>>   
>>>>
>>>> So:
>>>>
>>>> amlogic,boot-pages: 10
>>>> amlogic,boot-page-step: 3  
>>>
>>> Ok I get it. Thanks for the explanation. I don't really understand the
>>> logic behind it though. Do you know why the bootROM would access only
>>> one page over 2 or 3? Is there a default value? Is this configurable?  
>>
>> No, boot rom source is closed, I don't have access to it. I get this logic
>> from old version of vendor's uboot - in practice they use non 2 or 3, they
>> use hardcoded 128 step value. And amlogic,boot-pages is 1024
> 
> Feels like they are trying to use only the first page of each block, no?
> 
> That's very weird but I understand better.

A little bit no, they use every 128 page in range [0, 1024] pages. E.g. there will
be 8 such pages:
0
128
256
512
640
768
896
1024

They write some metadata about SoC to such pages.

Thanks, Arseniy

> 
> Thanks,
> Miquèl