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Message-ID: <20240507-b4-upstream-bootph-all-v1-4-c6d52651856f@ti.com>
Date: Tue, 7 May 2024 15:14:31 +0530
From: Manorit Chawdhry <m-chawdhry@...com>
To: Nishanth Menon <nm@...com>, Vignesh Raghavendra <vigneshr@...com>,
Tero
Kristo <kristo@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof
Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
CC: <linux-arm-kernel@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, Neha Malcom Francis <n-francis@...com>,
Aniket Limaye <a-limaye@...com>, Udit Kumar <u-kumar1@...com>,
Beleswar Padhi
<b-padhi@...com>, Manorit Chawdhry <m-chawdhry@...com>
Subject: [PATCH 4/5] arm64: dts: ti: k3-j721e*: Add bootph-* properties
Adds bootph-* properties to the leaf nodes to enable U-boot to
utilise them.
Signed-off-by: Manorit Chawdhry <m-chawdhry@...com>
---
.../arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 20 ++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 9 +++++++++
arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 17 +++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 5 +++++
5 files changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 8230d53cd696..ebc9ab3b6790 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -193,6 +193,7 @@ J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
>;
+ bootph-all;
};
main_uart1_pins_default: main-uart1-default-pins {
@@ -234,6 +235,7 @@ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
>;
+ bootph-all;
};
vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
@@ -247,6 +249,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>;
+ bootph-all;
};
main_usbss1_pins_default: main-usbss1-default-pins {
@@ -272,6 +275,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
>;
+ bootph-all;
};
main_i2c1_pins_default: main-i2c1-default-pins {
@@ -342,6 +346,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
>;
+ bootph-all;
};
mcu_uart0_pins_default: mcu-uart0-default-pins {
@@ -351,6 +356,7 @@ J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
+ bootph-all;
};
sw11_button_pins_default: sw11-button-default-pins {
@@ -370,6 +376,7 @@ J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
>;
+ bootph-all;
};
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
@@ -427,6 +434,7 @@ wkup_gpio_pins_default: wkup-gpio-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
>;
+ bootph-all;
};
};
@@ -435,12 +443,14 @@ &wkup_uart0 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
+ bootph-all;
};
&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
+ bootph-all;
};
&main_uart0 {
@@ -449,6 +459,7 @@ &main_uart0 {
pinctrl-0 = <&main_uart0_pins_default>;
/* Shared with ATF on this platform */
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+ bootph-all;
};
&main_uart1 {
@@ -473,6 +484,7 @@ &wkup_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_gpio_pins_default>;
+ bootph-all;
};
&main_gpio0 {
@@ -489,6 +501,7 @@ &main_sdhci0 {
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
+ bootph-all;
};
&main_sdhci1 {
@@ -500,10 +513,12 @@ &main_sdhci1 {
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
+ bootph-all;
};
&usb_serdes_mux {
idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
+ bootph-all;
};
&serdes_ln_ctrl {
@@ -513,6 +528,7 @@ &serdes_ln_ctrl {
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+ bootph-all;
};
&serdes_wiz3 {
@@ -534,6 +550,7 @@ &usbss0 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss0_pins_default>;
ti,vbus-divider;
+ bootph-all;
};
&usb0 {
@@ -541,6 +558,7 @@ &usb0 {
maximum-speed = "super-speed";
phys = <&serdes3_usb_link>;
phy-names = "cdns3,usb3-phy";
+ bootph-all;
};
&usbss1 {
@@ -569,6 +587,7 @@ flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
+ bootph-all;
partitions {
compatible = "fixed-partitions";
@@ -650,6 +669,7 @@ exp2: gpio@22 {
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
+ bootph-all;
p09-hog {
/* P11 - MCASP/TRACE_MUX_S0 */
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index c7eafbc862f9..cb8cf307be44 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -226,6 +226,7 @@ secure_proxy_main: mailbox@...00000 {
<0x00 0x32800000 0x00 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ bootph-all;
};
smmu0: iommu@...00000 {
@@ -2864,5 +2865,6 @@ main_esm: esm@...000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x700000 0x0 0x1000>;
ti,esm-pins = <344>, <345>;
+ bootph-all;
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index 4618b697fbc4..c9baf0460cba 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -21,16 +21,19 @@ dmsc: system-controller@...83000 {
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
+ bootph-all;
};
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
+ bootph-all;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
+ bootph-all;
};
};
@@ -57,6 +60,7 @@ wkup_conf: bus@...00000 {
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
+ bootph-all;
};
};
@@ -111,6 +115,7 @@ mcu_timer0: timer@...00000 {
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
+ bootph-pre-ram;
};
mcu_timer1: timer@...10000 {
@@ -469,6 +474,7 @@ mcu_ringacc: ringacc@...00000 {
ti,sci = <&dmsc>;
ti,sci-dev-id = <235>;
msi-parent = <&main_udmass_inta>;
+ bootph-all;
};
mcu_udmap: dma-controller@...c0000 {
@@ -493,6 +499,7 @@ mcu_udmap: dma-controller@...c0000 {
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>; /* RX_HCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+ bootph-all;
};
};
@@ -509,6 +516,7 @@ secure_proxy_mcu: mailbox@...80000 {
* firmware on non-MPU processors
*/
status = "disabled";
+ bootph-pre-ram;
};
mcu_cpsw: ethernet@...00000 {
@@ -681,6 +689,7 @@ wkup_vtm0: temperature-sensor@...40000 {
<0x00 0x43000300 0x00 0x10>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
+ bootph-pre-ram;
};
mcu_esm: esm@...00000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index 0c4575ad8d7c..a497e94b5b96 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -34,6 +34,7 @@ memory@...00000 {
/* 4G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000000 0x80000000>;
+ bootph-all;
};
reserved_memory: reserved-memory {
@@ -309,6 +310,7 @@ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
>;
+ bootph-all;
};
main_uart0_pins_default: main-uart0-default-pins {
@@ -353,12 +355,14 @@ main_usbss0_pins_default: main-usbss0-default-pins {
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>;
+ bootph-all;
};
main_usbss1_pins_default: main-usbss1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
>;
+ bootph-all;
};
main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins {
@@ -518,6 +522,7 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
>;
+ bootph-all;
};
vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
@@ -553,6 +558,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
>;
+ bootph-all;
};
/* Reset for M.2 M Key slot on PCIe1 */
@@ -568,6 +574,7 @@ &wkup_uart0 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
+ bootph-all;
};
&wkup_i2c0 {
@@ -732,6 +739,7 @@ &mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
+ bootph-all;
};
&main_uart0 {
@@ -740,6 +748,7 @@ &main_uart0 {
pinctrl-0 = <&main_uart0_pins_default>;
/* Shared with ATF on this platform */
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+ bootph-all;
};
&main_uart1 {
@@ -757,6 +766,7 @@ &main_sdhci1 {
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
+ bootph-all;
};
&ospi0 {
@@ -775,6 +785,7 @@ flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
+ bootph-all;
partitions {
compatible = "fixed-partitions";
@@ -914,6 +925,7 @@ &wkup_gpio0 {
&usb_serdes_mux {
idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
+ bootph-all;
};
&serdes_ln_ctrl {
@@ -923,6 +935,7 @@ &serdes_ln_ctrl {
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+ bootph-all;
};
&serdes_wiz3 {
@@ -962,6 +975,7 @@ &usbss0 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss0_pins_default>;
ti,vbus-divider;
+ bootph-all;
};
&usb0 {
@@ -969,6 +983,7 @@ &usb0 {
maximum-speed = "super-speed";
phys = <&serdes3_usb_link>;
phy-names = "cdns3,usb3-phy";
+ bootph-all;
};
&serdes2 {
@@ -985,6 +1000,7 @@ &usbss1 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss1_pins_default>;
ti,vbus-divider;
+ bootph-all;
};
&usb1 {
@@ -992,6 +1008,7 @@ &usb1 {
maximum-speed = "super-speed";
phys = <&serdes2_usb_link>;
phy-names = "cdns3,usb3-phy";
+ bootph-all;
};
&mcu_cpsw {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 1fae6495db07..37de479f9be8 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -150,6 +150,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
>;
+ bootph-all;
};
pmic_irq_pins_default: pmic-irq-default-pins {
@@ -172,6 +173,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
>;
+ bootph-all;
};
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
@@ -191,6 +193,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */
>;
+ bootph-all;
};
};
@@ -377,6 +380,7 @@ flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
+ bootph-all;
partitions {
compatible = "fixed-partitions";
@@ -439,6 +443,7 @@ &hbmc {
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x00 0x00 0x4000000>;
+ bootph-all;
partitions {
compatible = "fixed-partitions";
--
2.43.2
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