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Message-ID: <20240507095545.8210-3-r-gunasekaran@ti.com>
Date: Tue, 7 May 2024 15:25:45 +0530
From: Ravi Gunasekaran <r-gunasekaran@...com>
To: <nm@...com>, <vigneshr@...com>
CC: <kristo@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <srk@...com>, <rogerq@...nel.org>,
<r-gunasekaran@...com>, <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH v3 2/2] arm64: dts: ti: k3-j784s4-evm: Enable USB3 support
From: Matt Ranostay <mranostay@...com>
The board uses SERDES0 Lane 3 for USB3 IP. So update the
SerDes lane info for USB. Add the pin mux data and
enable USB3 support.
Signed-off-by: Matt Ranostay <mranostay@...com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@...com>
---
Changes since v2:
-----------------
* No change
Changes since v1:
----------------
* Fixed dtbs_check warning by renaming 'main-usbss0-pins-default'
to 'main-usbss0-default-pins'
v2: https://lore.kernel.org/all/20240506052044.8228-3-r-gunasekaran@ti.com/
v1: https://lore.kernel.org/all/20240502053615.29514-3-r-gunasekaran@ti.com/
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 41 ++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index d511b25d62e3..a2d3cba0423e 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -336,6 +336,13 @@
J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
>;
};
+
+ main_usbss0_pins_default: main-usbss0-default-pins {
+ bootph-all;
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */
+ >;
+ };
};
&wkup_pmx2 {
@@ -1041,6 +1048,40 @@
<&k3_clks 218 22>;
};
+&serdes0 {
+ status = "okay";
+
+ serdes0_usb_link: phy@3 {
+ reg = <3>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 4>;
+ };
+};
+
+&serdes_wiz0 {
+ status = "okay";
+};
+
+&usb_serdes_mux {
+ idle-states = <0>; /* USB0 to SERDES lane 3 */
+};
+
+&usbss0 {
+ status = "okay";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ pinctrl-names = "default";
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "super-speed";
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
&serdes_wiz4 {
status = "okay";
};
--
2.17.1
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