linux-kernel - RE: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension

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Message-ID: <DM8PR11MB5751A0943E23FE46AC4B7D89B8E52@DM8PR11MB5751.namprd11.prod.outlook.com>
Date: Wed, 8 May 2024 11:20:22 +0000
From: "Wang, Xiao W" <xiao.w.wang@...el.com>
To: Pu Lehui <pulehui@...wei.com>, "paul.walmsley@...ive.com"
	<paul.walmsley@...ive.com>, "palmer@...belt.com" <palmer@...belt.com>,
	"aou@...s.berkeley.edu" <aou@...s.berkeley.edu>, "luke.r.nels@...il.com"
	<luke.r.nels@...il.com>, "xi.wang@...il.com" <xi.wang@...il.com>,
	"bjorn@...nel.org" <bjorn@...nel.org>
CC: "ast@...nel.org" <ast@...nel.org>, "daniel@...earbox.net"
	<daniel@...earbox.net>, "andrii@...nel.org" <andrii@...nel.org>,
	"martin.lau@...ux.dev" <martin.lau@...ux.dev>, "eddyz87@...il.com"
	<eddyz87@...il.com>, "song@...nel.org" <song@...nel.org>,
	"yonghong.song@...ux.dev" <yonghong.song@...ux.dev>,
	"john.fastabend@...il.com" <john.fastabend@...il.com>, "kpsingh@...nel.org"
	<kpsingh@...nel.org>, "sdf@...gle.com" <sdf@...gle.com>, "haoluo@...gle.com"
	<haoluo@...gle.com>, "jolsa@...nel.org" <jolsa@...nel.org>,
	"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"bpf@...r.kernel.org" <bpf@...r.kernel.org>, "Li, Haicheng"
	<haicheng.li@...el.com>
Subject: RE: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension



> -----Original Message-----
> From: Pu Lehui <pulehui@...wei.com>
> Sent: Tuesday, May 7, 2024 8:47 PM
> To: Wang, Xiao W <xiao.w.wang@...el.com>; paul.walmsley@...ive.com;
> palmer@...belt.com; aou@...s.berkeley.edu; luke.r.nels@...il.com;
> xi.wang@...il.com; bjorn@...nel.org
> Cc: ast@...nel.org; daniel@...earbox.net; andrii@...nel.org;
> martin.lau@...ux.dev; eddyz87@...il.com; song@...nel.org;
> yonghong.song@...ux.dev; john.fastabend@...il.com; kpsingh@...nel.org;
> sdf@...gle.com; haoluo@...gle.com; jolsa@...nel.org; linux-
> riscv@...ts.infradead.org; linux-kernel@...r.kernel.org; bpf@...r.kernel.org;
> Li, Haicheng <haicheng.li@...el.com>
> Subject: Re: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension
> 
> 
> On 2024/5/7 18:45, Xiao Wang wrote:
> > The Zba extension provides add.uw insn which can be used to implement
> > zext.w with rs2 set as ZERO.
> >
> > Signed-off-by: Xiao Wang <xiao.w.wang@...el.com>
> > ---
> >   arch/riscv/Kconfig       | 19 +++++++++++++++++++
> >   arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
> >   2 files changed, 37 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 6bec1bce6586..0679127cc0ea 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
> >   	  preemption. Enabling this config will result in higher memory
> >   	  consumption due to the allocation of per-task's kernel Vector
> context.
> >
> > +config TOOLCHAIN_HAS_ZBA
> > +	bool
> > +	default y
> > +	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
> > +	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
> > +	depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
> > +	depends on AS_HAS_OPTION_ARCH
> > +
> >   config TOOLCHAIN_HAS_ZBB
> >   	bool
> >   	default y
> > @@ -601,6 +609,17 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
> >   	def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
> >   	depends on AS_HAS_OPTION_ARCH
> >
> > +config RISCV_ISA_ZBA
> > +	bool "Zba extension support for bit manipulation instructions"
> > +	depends on TOOLCHAIN_HAS_ZBA
> > +	depends on RISCV_ALTERNATIVE
> > +	default y
> > +	help
> > +	   Adds support to dynamically detect the presence of the ZBA
> > +	   extension (address generation acceleration) and enable its usage.
> 
> It would be better to add Zba's function description like Zbb.

OK, would add some description on next version.

Thanks,
Xiao

> 
> > +
> > +	   If you don't know what to do here, say Y.
> > +
> >   config RISCV_ISA_ZBB
> >   	bool "Zbb extension support for bit manipulation instructions"
> >   	depends on TOOLCHAIN_HAS_ZBB
> > diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
> > index f4b6b3b9edda..18a7885ba95e 100644
> > --- a/arch/riscv/net/bpf_jit.h
> > +++ b/arch/riscv/net/bpf_jit.h
> > @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void)
> >   	return IS_ENABLED(CONFIG_RISCV_ISA_C);
> >   }
> >
> > +static inline bool rvzba_enabled(void)
> > +{
> > +	return IS_ENABLED(CONFIG_RISCV_ISA_ZBA) &&
> riscv_has_extension_likely(RISCV_ISA_EXT_ZBA);
> > +}
> > +
> >   static inline bool rvzbb_enabled(void)
> >   {
> >   	return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
> riscv_has_extension_likely(RISCV_ISA_EXT_ZBB);
> > @@ -937,6 +942,14 @@ static inline u16 rvc_sdsp(u32 imm9, u8 rs2)
> >   	return rv_css_insn(0x7, imm, rs2, 0x2);
> >   }
> >
> > +/* RV64-only ZBA instructions. */
> > +
> > +static inline u32 rvzba_zextw(u8 rd, u8 rs1)
> > +{
> > +	/* add.uw rd, rs1, ZERO */
> > +	return rv_r_insn(0x04, RV_REG_ZERO, rs1, 0, rd, 0x3b);
> > +}
> > +
> >   #endif /* __riscv_xlen == 64 */
> >
> >   /* Helper functions that emit RVC instructions when possible. */
> > @@ -1159,6 +1172,11 @@ static inline void emit_zexth(u8 rd, u8 rs, struct
> rv_jit_context *ctx)
> >
> >   static inline void emit_zextw(u8 rd, u8 rs, struct rv_jit_context *ctx)
> >   {
> > +	if (rvzba_enabled()) {
> > +		emit(rvzba_zextw(rd, rs), ctx);
> > +		return;
> > +	}
> 
> Looks good to me. It seems that Zba has fewer uses in rv64 bpf jit.
> 
> > +
> >   	emit_slli(rd, rs, 32, ctx);
> >   	emit_srli(rd, rd, 32, ctx);
> >   }