| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Thu, 9 May 2024 08:00:00 +0800
From: Andy Chiu <andy.chiu@...ive.com>
To: Deepak Gupta <debug@...osinc.com>
Cc: paul.walmsley@...ive.com, rick.p.edgecombe@...el.com, broonie@...nel.org,
Szabolcs.Nagy@....com, kito.cheng@...ive.com, keescook@...omium.org,
ajones@...tanamicro.com, conor.dooley@...rochip.com, cleger@...osinc.com,
atishp@...shpatra.org, alex@...ti.fr, bjorn@...osinc.com,
alexghiti@...osinc.com, samuel.holland@...ive.com, conor@...nel.org,
linux-doc@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, linux-mm@...ck.org,
linux-arch@...r.kernel.org, linux-kselftest@...r.kernel.org, corbet@....net,
palmer@...belt.com, aou@...s.berkeley.edu, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, oleg@...hat.com, akpm@...ux-foundation.org,
arnd@...db.de, ebiederm@...ssion.com, Liam.Howlett@...cle.com, vbabka@...e.cz,
lstoakes@...il.com, shuah@...nel.org, brauner@...nel.org,
jerry.shih@...ive.com, hankuan.chen@...ive.com, greentime.hu@...ive.com,
evan@...osinc.com, xiao.w.wang@...el.com, charlie@...osinc.com,
apatel@...tanamicro.com, mchitale@...tanamicro.com, dbarboza@...tanamicro.com,
sameo@...osinc.com, shikemeng@...weicloud.com, willy@...radead.org,
vincent.chen@...ive.com, guoren@...nel.org, samitolvanen@...gle.com,
songshuaishuai@...ylab.org, gerg@...nel.org, heiko@...ech.de, bhe@...hat.com,
jeeheng.sia@...rfivetech.com, cyy@...self.name, maskray@...gle.com,
ancientmodern4@...il.com, mathis.salmen@...sal.de, cuiyunhui@...edance.com,
bgray@...ux.ibm.com, mpe@...erman.id.au, baruch@...s.co.il, alx@...nel.org,
david@...hat.com, catalin.marinas@....com, revest@...omium.org,
josh@...htriplett.org, shr@...kernel.io, deller@....de, omosnace@...hat.com,
ojeda@...nel.org, jhubbard@...dia.com
Subject: Re: [PATCH v3 05/29] riscv: zicfiss / zicfilp enumeration
Hi Deepak,
On Thu, Apr 4, 2024 at 7:41 AM Deepak Gupta <debug@...osinc.com> wrote:
>
> This patch adds support for detecting zicfiss and zicfilp. zicfiss and
> zicfilp stands for unprivleged integer spec extension for shadow stack
> and branch tracking on indirect branches, respectively.
>
> This patch looks for zicfiss and zicfilp in device tree and accordinlgy
> lights up bit in cpu feature bitmap. Furthermore this patch adds detection
> utility functions to return whether shadow stack or landing pads are
> supported by cpu.
>
> Signed-off-by: Deepak Gupta <debug@...osinc.com>
> ---
> arch/riscv/include/asm/cpufeature.h | 13 +++++++++++++
> arch/riscv/include/asm/hwcap.h | 2 ++
> arch/riscv/include/asm/processor.h | 1 +
> arch/riscv/kernel/cpufeature.c | 2 ++
> 4 files changed, 18 insertions(+)
>
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> index 0bd11862b760..f0fb8d8ae273 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -8,6 +8,7 @@
>
> #include <linux/bitmap.h>
> #include <linux/jump_label.h>
> +#include <linux/smp.h>
> #include <asm/hwcap.h>
> #include <asm/alternative-macros.h>
> #include <asm/errno.h>
> @@ -137,4 +138,16 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi
>
> DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key);
>
> +static inline bool cpu_supports_shadow_stack(void)
> +{
> + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) &&
> + riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFISS));
> +}
> +
> +static inline bool cpu_supports_indirect_br_lp_instr(void)
> +{
> + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) &&
> + riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFILP));
> +}
> +
> #endif
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 1f2d2599c655..74b6c727f545 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -80,6 +80,8 @@
> #define RISCV_ISA_EXT_ZFA 71
> #define RISCV_ISA_EXT_ZTSO 72
> #define RISCV_ISA_EXT_ZACAS 73
nit: two tabs for alignment
> +#define RISCV_ISA_EXT_ZICFILP 74
> +#define RISCV_ISA_EXT_ZICFISS 75
>
> #define RISCV_ISA_EXT_XLINUXENVCFG 127
>
> diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> index a8509cc31ab2..6c5b3d928b12 100644
> --- a/arch/riscv/include/asm/processor.h
> +++ b/arch/riscv/include/asm/processor.h
> @@ -13,6 +13,7 @@
> #include <vdso/processor.h>
>
> #include <asm/ptrace.h>
> +#include <asm/hwcap.h>
>
> #ifdef CONFIG_64BIT
> #define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1))
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 79a5a35fab96..d052cad5b82f 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -263,6 +263,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
> __RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts),
> __RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts),
> + __RISCV_ISA_EXT_SUPERSET(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xlinuxenvcfg_exts),
> + __RISCV_ISA_EXT_SUPERSET(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_xlinuxenvcfg_exts),
> __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
> __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
> __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
> --
> 2.43.2
>
Thanks,
Andy
Powered by blists - more mailing lists