linux-kernel - Re: [External] Re: [PATCH v5 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

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Message-ID: <CAEEQ3wkHc-EaRPKLivZoxO6jKXv9bigbYhacWouL7+KbgbwWpQ@mail.gmail.com>
Date: Fri, 10 May 2024 17:09:28 +0800
From: yunhui cui <cuiyunhui@...edance.com>
To: Sudeep Holla <sudeep.holla@....com>, Palmer Dabbelt <palmer@...belt.com>
Cc: rafael@...nel.org, lenb@...nel.org, linux-acpi@...r.kernel.org, 
	linux-kernel@...r.kernel.org, paul.walmsley@...ive.com, 
	sunilvl@...tanamicro.com, aou@...s.berkeley.edu, 
	linux-riscv@...ts.infradead.org, bhelgaas@...gle.com, james.morse@....com, 
	jhugo@...eaurora.org, jeremy.linton@....com, john.garry@...wei.com, 
	Jonathan.Cameron@...wei.com, pierre.gondois@....com, tiantao6@...wei.com, 
	Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [External] Re: [PATCH v5 2/3] riscv: cacheinfo: initialize
 cacheinfo's level and type from ACPI PPTT

Hi Palmer,

There are already related Reviewed-by, Gentle ping...

On Thu, May 9, 2024 at 11:27 PM Sudeep Holla <sudeep.holla@....com> wrote:
>
> On Thu, May 09, 2024 at 03:32:59PM +0800, Yunhui Cui wrote:
> > Before cacheinfo can be built correctly, we need to initialize level
> > and type. Since RISC-V currently does not have a register group that
> > describes cache-related attributes like ARM64, we cannot obtain them
> > directly, so now we obtain cache leaves from the ACPI PPTT table
> > (acpi_get_cache_info()) and set the cache type through split_levels.
> >
> > Suggested-by: Jeremy Linton <jeremy.linton@....com>
> > Suggested-by: Sudeep Holla <sudeep.holla@....com>
>
> I am not sure why you have not added my reviewed-by as I was happy with
> v3 onwards IIRC. Anyways, I will give it again 😄
>
> Reviewed-by: Sudeep Holla <sudeep.holla@....com>
>
> --
> Regards,
> Sudeep

Thanks，
Yunhui