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Message-ID: <20240511130349.23409-5-ansuelsmth@gmail.com>
Date: Sat, 11 May 2024 15:03:48 +0200
From: Christian Marangi <ansuelsmth@...il.com>
To: Hauke Mehrtens <hauke@...ke-m.de>,
Rafał Miłecki <zajec5@...il.com>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Florian Fainelli <florian.fainelli@...adcom.com>,
Broadcom internal kernel review list <bcm-kernel-feedback-list@...adcom.com>,
Christian Marangi <ansuelsmth@...il.com>,
linux-mips@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Daniel González Cabanelas <dgcbueu@...il.com>,
Álvaro Fernández Rojas <noltari@...il.com>
Subject: [PATCH v5 4/4] mips: bmips: enable RAC on BMIPS4350
From: Daniel González Cabanelas <dgcbueu@...il.com>
The data RAC is left disabled by the bootloader in some SoCs, at least in
the core it boots from.
Enabling this feature increases the performance up to +30% depending on the
task.
Signed-off-by: Daniel González Cabanelas <dgcbueu@...il.com>
Signed-off-by: Álvaro Fernández Rojas <noltari@...il.com>
[ rework code and reduce code duplication ]
Signed-off-by: Christian Marangi <ansuelsmth@...il.com>
Acked-by: Florian Fainelli <florian.fainelli@...adcom.com>
---
arch/mips/kernel/smp-bmips.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 20e2fb10022d..52324738cbb3 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -626,6 +626,23 @@ void bmips_cpu_setup(void)
__raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
break;
+ case CPU_BMIPS4350:
+ u32 rac_addr = BMIPS_RAC_CONFIG_1;
+
+ if (!(read_c0_brcm_cmt_local() & (1 << 31)))
+ rac_addr = BMIPS_RAC_CONFIG;
+
+ /* Enable data RAC */
+ cfg = __raw_readl(cbr + rac_addr);
+ __raw_writel(cfg | 0xf, cbr + rac_addr);
+ __raw_readl(cbr + rac_addr);
+
+ /* Flush stale data out of the readahead cache */
+ cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
+ __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
+ __raw_readl(cbr + BMIPS_RAC_CONFIG);
+ break;
+
case CPU_BMIPS4380:
/* CBG workaround for early BMIPS4380 CPUs */
switch (read_c0_prid()) {
--
2.43.0
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